公开(公告)号：US11204897B2

公开(公告)日：2021-12-21

申请号：US16669320

申请日：2019-10-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Fu An Tien ,  Changsheng Ying ,  Hsu-Ting Huang ,  Ru-Gun Liu

IPC: G06F16/174 ,  G06F16/16 ,  G06F30/392 ,  G06F30/34 ,  G06F30/36 ,  G06F30/39

Abstract: A computer-implemented method includes executing, using a computer, a process including a main thread that receives a layout file. The layout file includes a first plurality of tags and compressed information blocks. Each tag of the first plurality is associated with a compressed information block. The method further includes decompressing the compressed information blocks using sub-threads and thereby obtaining decompressed information blocks. The sub-threads are created by the main thread, and each sub-thread corresponds to a compressed information block. The decompressed information blocks are combined into decompressed layout information. The decompressed file is partitioned and each partition is provided to a node of a distributed computing system for performing layout correction. Multiple result files each in a compressed format are obtained from the distributed computing system and the result files are combined to obtain a single result file without decompressing and re-compressing the results from the distributed computing system.

公开(公告)号：US11093683B2

公开(公告)日：2021-08-17

申请号：US16559097

申请日：2019-09-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fu-An Tien ,  Hsu-Ting Huang ,  Ru-Gun Liu

IPC: G06F30/398 ,  G06F30/394

Abstract: Systems and methods are provided for generating test patterns. In various embodiments, systems and methods are provided in which machine learning is utilized to generate the test patterns in a manner so that the test patterns conform with design rule check (DRC) specified for a particular semiconductor manufacturing process or for particular types of devices. A test pattern generation system includes test pattern generation circuitry which receives a noise image. The test pattern generation generates a pattern image based on the noise image, and further generates a test pattern based on the pattern image. The test pattern is representative of geometric shapes of an electronic device design layout that is free of design rule check violations.

公开(公告)号：US20190094680A1

公开(公告)日：2019-03-28

申请号：US15813774

申请日：2017-11-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsu-Ting Huang ,  Chih-Shiang Chou ,  Ru-Gun Liu

IPC: G03F1/36 ,  G06F17/50 ,  H01L21/027 ,  H01L21/66 ,  G03F1/78 ,  G03F1/80 ,  G03F7/16 ,  G03F7/20 ,  G03F7/38 ,  G03F7/26

Abstract: The present disclosure provides an integrated circuit (IC) method in accordance with some embodiments. The method includes building a mask model to simulate a mask image and a compound lithography computational model to simulate a wafer pattern; calibrating the mask model using a measured mask image; calibrating the compound lithography computational model using a measured wafer data and the calibrated mask model; and performing an optical proximity correction (OPC) process to an IC pattern using the calibrated compound computational model, thereby generating a mask pattern for mask fabrication.

公开(公告)号：US20180285512A1

公开(公告)日：2018-10-04

申请号：US15997513

申请日：2018-06-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsu-Ting Huang ,  Shuo-Yen Chou ,  Ru-Gun Liu

IPC: G06F17/50 ,  G03F1/78

CPC classification number: G06F17/5081 ,  G03F1/70 ,  G03F1/78 ,  G06F17/5068 ,  G06F2217/12

Abstract: Source beam optimization (SBO) methods are disclosed herein for enhancing lithography printability. An exemplary method includes receiving an IC design layout and performing an SBO process using the IC design layout to generate a mask shot map and an illumination source map. The SBO process uses an SBO model that collectively simulates a mask making process using the mask shot mask and a wafer making process using the illumination source map. A mask can be fabricated using the mask shot map, and a wafer can be fabricated using the illumination source map (and, in some implementations, using the mask fabricated using the mask shot map). The wafer includes a final wafer pattern that corresponds with a target wafer pattern defined by the IC design layout. SBO methods disclosed herein can significantly reduce (or eliminate) variances between the final wafer pattern and the target wafer pattern.

公开(公告)号：US11415890B2

公开(公告)日：2022-08-16

申请号：US17195469

申请日：2021-03-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hsu-Ting Huang ,  Shih-Hsiang Lo ,  Ru-Gun Liu

IPC: G03F7/20 ,  G03F1/36 ,  G03F1/78

Abstract: A method for mask data synthesis and mask making includes calibrating an optical proximity correction (OPC) model by adjusting a plurality of parameters including a first parameter and a second parameter, wherein the first parameter indicates a long-range effect caused by an electron-beam lithography tool for making a mask used to manufacture a structure, and the second parameter indicates a geometric feature of a structure or a manufacturing process to make the structure, generating a device layout, calculating a first grid pattern density map of the device layout, generating a long-range correction map, at least based on the calibrated OPC model and the first grid pattern density map of the device layout, and performing an OPC to generate a corrected mask layout, at least based on the generated long-range correction map and the calibrated OPC model.

公开(公告)号：US11080458B2

公开(公告)日：2021-08-03

申请号：US16584396

申请日：2019-09-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Fu An Tien ,  Hsu-Ting Huang ,  Ru-Gun Liu ,  Shih-Hsiang Lo

IPC: G06F30/30 ,  G06F30/398 ,  G03F7/20 ,  G01N21/95 ,  G03F1/36 ,  G06F30/3308 ,  G06F30/337 ,  G06F30/20 ,  G06F119/18 ,  G03F1/70

Abstract: In a method of optimizing a lithography model in a lithography simulation, a mask is formed in accordance with a given layout, a wafer is printed using the mask, a pattern formed on the printed wafer is measured, a wafer pattern is simulated using a wafer edge bias table and the given mask layout, a difference between the simulated wafer pattern and the measured pattern is obtained, and the wafer edge table is adjusted according to the difference.

公开(公告)号：US11061318B2

公开(公告)日：2021-07-13

申请号：US16748551

申请日：2020-01-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Hsiang Lo ,  Hsu-Ting Huang ,  Ru-Gun Liu

IPC: G06F111/06 ,  G06F111/10 ,  G03F1/36 ,  G03F1/70 ,  H01L21/027 ,  G03F7/20

Abstract: Provided is a method for fabricating a semiconductor device including generating an ideal image using measured contour data and fitted conventional model terms. The method further includes using the fitted conventional model terms and a mask layout to provide a conventional model aerial image. In some embodiments, the method further includes generating a plurality of mask raster images using the mask layout, where the plurality of mask raster images is generated for each measurement site of the measured contour data. In various embodiments, the method also include training a neural network to mimic the ideal image, where the generated ideal image provides a target output of the neural network, and where the conventional model aerial image and the plurality of mask raster images provide inputs to the neural network.

公开(公告)号：US10962875B2

公开(公告)日：2021-03-30

申请号：US16700336

申请日：2019-12-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsu-Ting Huang ,  Chih-Shiang Chou ,  Ru-Gun Liu

IPC: G03F1/36 ,  G03F1/80 ,  G03F7/16 ,  G03F7/20 ,  G03F7/38 ,  G03F7/26 ,  G03F1/78 ,  H01L21/027 ,  H01L21/66 ,  G06F30/20 ,  G06F30/398 ,  G06F119/18

Abstract: An integrated circuit (IC) method is provided. The method includes building a mask model to simulate an aerial mask image of a mask, and a compound lithography computational (CLC) model to simulate a wafer pattern; calibrating the mask model using a measured aerial mask image of the mask; calibrating the CLC model using measured wafer data and the calibrated mask model; performing an optical proximity correction (OPC) process to a mask pattern using the calibrated CLC model, thereby generating a corrected mask pattern for mask fabrication. Alternatively, the method includes measuring a mask image of a mask optically projected on a wafer with an instrument; calibrating a mask model using the measured mask image; calibrating a CLC model using measured wafer data and the calibrated mask model; and performing an OPC process to a mask pattern using the calibrated CLC model, thereby generating a corrected mask pattern for mask fabrication.

公开(公告)号：US10417376B2

公开(公告)日：2019-09-17

申请号：US15997513

申请日：2018-06-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsu-Ting Huang ,  Shuo-Yen Chou ,  Ru-Gun Liu

IPC: G06F17/50 ,  G03F1/78 ,  G03F1/70

Abstract: Source beam optimization (SBO) methods are disclosed herein for enhancing lithography printability. An exemplary method includes receiving an integrated circuit (IC) design layout and performing an SBO process using the IC design layout to generate a mask shot map and an illumination source map. The SBO process uses an SBO model that collectively simulates a mask making process using the mask shot map and a wafer making process using the illumination source map. A mask can be fabricated using the mask shot map, and a wafer can be fabricated using the illumination source map (and, in some implementations, using the mask fabricated using the mask shot map). The wafer includes a final wafer pattern that corresponds with a target wafer pattern defined by the IC design layout. The SBO methods disclosed herein can significantly reduce (or eliminate) variances between the final wafer pattern and the target wafer pattern.