公开(公告)号：US11145564B2

公开(公告)日：2021-10-12

申请号：US16395435

申请日：2019-04-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Fan Huang ,  Hui-Chi Chen ,  Kuo-Chin Chang ,  Dian-Hau Chen ,  Yen-Ming Chen

IPC: H01L23/31 ,  H01L23/29 ,  H01L23/00 ,  H01L21/56

Abstract: Semiconductor devices, integrated circuits and methods of forming the same are provided. In one embodiment, a method for integrated circuit (IC) fabrication includes forming a passivation layer over a first contact feature, forming a second contact feature over and through the passivation layer to electrically connect to the first contact feature, and forming a multi-layer passivation structure over the second contact feature and over the passivation layer. Forming the multi-layer passivation structure includes depositing a first nitride layer, an oxide layer over the first nitride layer, and a second nitride layer over the oxide layer.

公开(公告)号：US10529824B2

公开(公告)日：2020-01-07

申请号：US16049545

申请日：2018-07-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yao-De Chiou ,  Hui-Chi Chen ,  Jeng-Ya Yeh

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/49 ,  H01L21/8234 ,  H01L21/8238

Abstract: A semiconductor device includes a first field effect transistor (FET) including a first gate dielectric layer and a first gate electrode. The first gate electrode includes a first lower metal layer and a first upper metal layer. The first lower metal layer includes a first underlying metal layer in contact with the first gate dielectric layer and a first bulk metal layer. A bottom of the first upper metal layer is in contact with an upper surface of the first underlying metal layer and an upper surface of the first bulk metal layer.

公开(公告)号：US20240213305A1

公开(公告)日：2024-06-27

申请号：US18594864

申请日：2024-03-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Fan Huang ,  Hung-Chao Kao ,  Yuan-Yang Hsiao ,  Tsung-Chieh Hsiao ,  Hsiang-Ku Shen ,  Hui-Chi Chen ,  Dian-Hau Chen ,  Yen-Ming Chen

IPC: H01G4/005 ,  H01L21/311 ,  H01L21/768 ,  H01L23/522 ,  H10B61/00

CPC classification number: H01L28/60 ,  H01L21/31116 ,  H01L21/76804 ,  H01L21/76805 ,  H01L23/5226 ,  H10B61/10

Abstract: The present disclosure is directed to a semiconductor device. The semiconductor device includes a multi-layer interconnect structure disposed over a substrate, a dielectric layer disposed over the multi-layer interconnect structure, and a metal-insulator-metal (MIM) capacitor disposed over the dielectric layer. The MIM capacitor includes a bottom electrode disposed on a top surface of the dielectric layer, a top electrode disposed above the bottom electrode, and an insulating layer interposed between the bottom electrode and the top electrode. The bottom electrode has a slanted sidewall with respect to the top surface of the dielectric layer. The top electrode has a vertical sidewall with respect to the top surface of the dielectric layer. The insulating layer covers the slanted sidewall of the bottom electrode.

公开(公告)号：US12022643B2

公开(公告)日：2024-06-25

申请号：US17036418

申请日：2020-09-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Yu Hsu ,  Jian-Hao Chen ,  Chia-Wei Chen ,  Shan-Mei Liao ,  Hui-Chi Chen ,  Yu-Chia Liang ,  Shih-Hao Lin ,  Kuei-Lun Lin ,  Kuo-Feng Yu ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC: H01L27/11 ,  H10B10/00

CPC classification number: H10B10/12

Abstract: A transistor includes a gate structure that has a first gate dielectric layer and a second gate dielectric layer. The first gate dielectric layer is disposed over the substrate. The first gate dielectric layer contains a first type of dielectric material that has a first dielectric constant. The second gate dielectric layer is disposed over the first gate dielectric layer. The second gate dielectric layer contains a second type of dielectric material that has a second dielectric constant. The second dielectric constant is greater than the first dielectric constant. The first dielectric constant and the second dielectric constant are each greater than a dielectric constant of silicon oxide.

公开(公告)号：US11521970B2

公开(公告)日：2022-12-06

申请号：US17063243

申请日：2020-10-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hsiang-Ku Shen ,  Chih Wei Lu ,  Hui-Chi Chen ,  Jeng-Ya David Yeh

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/08 ,  H01L21/768 ,  H01L29/51 ,  H01L29/49

Abstract: In a method of manufacturing a semiconductor device, first and second gate structures are formed. The first (second) gate structure includes a first (second) gate electrode layer and first (second) sidewall spacers disposed on both side faces of the first (second) gate electrode layer. The first and second gate electrode layers are recessed and the first and second sidewall spacers are recessed, thereby forming a first space and a second space over the recessed first and second gate electrode layers and first and second sidewall spacers, respectively. First and second protective layers are formed in the first and second spaces, respectively. First and second etch-stop layers are formed on the first and second protective layers, respectively. A first depth of the first space above the first sidewall spacers is different from a second depth of the first space above the first gate electrode layer.

公开(公告)号：US11437331B2

公开(公告)日：2022-09-06

申请号：US16655998

申请日：2019-10-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Fan Huang ,  Mao-Nan Wang ,  Hui-Chi Chen ,  Dian-Hau Chen ,  Yen-Ming Chen

IPC: H01L23/00

Abstract: A chip structure is provided. The chip structure includes a semiconductor substrate. The chip structure includes a first dielectric layer over the semiconductor substrate. The chip structure includes a first conductive layer over the first dielectric layer. The chip structure includes a second dielectric layer over the first conductive layer and the first dielectric layer. The chip structure includes a first conductive via passing through the second dielectric layer, the first conductive layer, and the first dielectric layer and electrically connected to the first conductive layer. The chip structure includes a second conductive via passing through the second dielectric layer and the first dielectric layer. The chip structure includes a first conductive pad over and in direct contact with the first conductive via. The chip structure includes a second conductive pad over and in direct contact with the second conductive via.

公开(公告)号：US11031458B2

公开(公告)日：2021-06-08

申请号：US16593078

申请日：2019-10-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Fan Huang ,  Chih-Yang Pai ,  Yuan-Yang Hsiao ,  Tsung-Chieh Hsiao ,  Hui-Chi Chen ,  Dian-Hau Chen ,  Yen-Ming Chen

IPC: H01L49/02 ,  H01L23/64 ,  H01G4/10 ,  H01G4/012

Abstract: A metal-insulator-metal (MIM) capacitor structure and a method for forming the same are provided. The MIM capacitor structure includes a substrate, and the substrate includes a capacitor region and a non-capacitor region. The MIM capacitor structure includes a first electrode layer formed over the substrate, and a first spacer formed on a sidewall of the first electrode layer. The MIM capacitor structure includes a first dielectric layer formed on the first spacers, and a second electrode layer formed on the first dielectric layer. The second electrode layer extends from the capacitor region to the non-capacitor region, and the second electrode layer extends beyond an outer sidewall of the first spacer.

公开(公告)号：US10468478B2

公开(公告)日：2019-11-05

申请号：US15794139

申请日：2017-10-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Fan Huang ,  Chih-Yang Pai ,  Yuan-Yang Hsiao ,  Tsung-Chieh Hsiao ,  Hui-Chi Chen ,  Dian-Hau Chen ,  Yen-Ming Chen

IPC: H01L49/02 ,  H01L23/64 ,  H01G4/10 ,  H01G4/012

Abstract: A metal-insulator-metal (MIM) capacitor structure and a method for forming the same are provided. The MIM capacitor structure includes a substrate, a bottom electrode layer, a first dielectric layer, a top electrode layer and first dielectric spacers. The bottom electrode layer is positioned over the substrate. The first dielectric layer is positioned over the bottom electrode layer. The top electrode layer is positioned over the first dielectric layer. The first dielectric spacers are positioned on opposite sidewalls of the bottom electrode layer. The first dielectric layer has a first dielectric constant. The first dielectric spacers have a second dielectric constant that is lower than the first dielectric constant.

公开(公告)号：US10163704B2

公开(公告)日：2018-12-25

申请号：US15180907

申请日：2016-06-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hui-Chi Chen ,  Hsiang-ku Shen ,  Jeng-Ya David Yeh

IPC: H01L21/70 ,  H01L21/768 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device includes a first gate structure disposed on a substrate and extending in a first direction. The first gate structure includes a first gate electrode, a first cap insulating layer disposed over the first gate electrode, first sidewall spacers disposed on opposing side faces of the first gate electrode and the first cap insulating layer and second sidewall spacers disposed over the first sidewall spacers. The semiconductor device further includes a first protective layer formed over the first cap insulating layer, the first sidewall spacers and the second sidewall spacers. The first protective layer has a π-shape having a head portion and two leg portions in a cross section along a second direction perpendicular to the first direction.

公开(公告)号：US20250140722A1

公开(公告)日：2025-05-01

申请号：US19004946

申请日：2024-12-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Fan Huang ,  Yen-Ming Chen ,  Chih-Sheng Li ,  Hui-Chi Chen ,  Chih-Hung Lu ,  Dian-Hau Chen

IPC: H01L23/00 ,  H01L21/02

Abstract: Semiconductor devices, integrated circuits and methods of forming the same are provided. In one embodiment, a method includes depositing a first dielectric layer over a metal pad disposed over a workpiece, forming a first opening in the first dielectric layer to expose a portion of the metal pad, after the forming of the first opening, forming a second dielectric layer over the exposed portion of the metal pad, depositing a first polymeric material over the second dielectric layer, forming a second opening through the first polymeric material and the second dielectric layer to expose the metal pad, and forming a bump feature over the exposed metal pad.