公开(公告)号：US20240312885A1

公开(公告)日：2024-09-19

申请号：US18672485

申请日：2024-05-23

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Hsiang-Ku Shen ,  Chun-Li Lin ,  Dian-Hau Chen

IPC分类号： H01L23/498 ,  H01L21/02 ,  H01L21/48 ,  H01L23/532

CPC分类号： H01L23/49811 ,  H01L21/02274 ,  H01L21/486 ,  H01L23/53219 ,  H01L23/53233 ,  H01L23/53295

摘要： Semiconductor devices and methods of forming the same are provided. In one embodiment, a semiconductor device includes a redistribution layer including a first conductive feature and a second conductive feature, a first contact feature disposed over and electrically coupled to the first conductive feature, a second contact feature disposed over and electrically coupled to the second conductive feature, and a passivation feature extending from between the first conductive feature and the second conductive feature between the first contact feature and the second contact feature. The passivation feature includes a dielectric feature and a dielectric layer. The dielectric layer is disposed on a planar top surface of the dielectric feature and a composition of the dielectric feature is different from a composition of the dielectric layer.

公开(公告)号：US11996356B2

公开(公告)日：2024-05-28

申请号：US18329327

申请日：2023-06-05

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Hsiang-Ku Shen ,  Chun-Li Lin ,  Dian-Hau Chen

IPC分类号： H01L23/495 ,  H01L21/02 ,  H01L21/48 ,  H01L23/498 ,  H01L23/532

CPC分类号： H01L23/49811 ,  H01L21/02274 ,  H01L21/486 ,  H01L23/53219 ,  H01L23/53233 ,  H01L23/53295

摘要： Semiconductor devices and methods of forming the same are provided. In one embodiment, a semiconductor device includes a redistribution layer including a first conductive feature and a second conductive feature, a first contact feature disposed over and electrically coupled to the first conductive feature, a second contact feature disposed over and electrically coupled to the second conductive feature, and a passivation feature extending from between the first conductive feature and the second conductive feature between the first contact feature and the second contact feature. The passivation feature includes a dielectric feature and a dielectric layer. The dielectric layer is disposed on a planar top surface of the dielectric feature and a composition of the dielectric feature is different from a composition of the dielectric layer.

公开(公告)号：US11716910B2

公开(公告)日：2023-08-01

申请号：US17002098

申请日：2020-08-25

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chih-Fan Huang ,  Hsiang-Ku Shen ,  Liang-Wei Wang ,  Chen-Chiu Huang ,  Dian-Hau Chen ,  Yen-Ming Chen

IPC分类号： H10N50/80 ,  H10B61/00 ,  H10N50/01

CPC分类号： H10N50/80 ,  H10B61/22 ,  H10N50/01

摘要： Semiconductor device and methods of forming the same are provided. A semiconductor device according to one embodiment includes a dielectric layer including a top surface, a plurality of magneto-resistive memory cells disposed in the dielectric layer and including top electrodes, a first etch stop layer disposed over the dielectric layer, a common electrode extending through the first etch stop layer to be in direct contact with the top electrodes, and a second etch slop layer disposed on the first etch stop layer and the common electrode. Top surfaces of the top electrodes are coplanar with the top surface of the dielectric layer.

公开(公告)号：US11443984B2

公开(公告)日：2022-09-13

申请号：US16983018

申请日：2020-08-03

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Hui-Chi Chen ,  Hsiang-Ku Shen ,  Jeng-Ya Yeh

IPC分类号： H01L27/088 ,  H01L21/768 ,  H01L29/66 ,  H01L29/78

摘要： A semiconductor device includes a first gate structure disposed on a substrate and extending in a first direction. The first gate structure includes a first gate electrode, a first cap insulating layer disposed over the first gate electrode, first sidewall spacers disposed on opposing side faces of the first gate electrode and the first cap insulating layer and second sidewall spacers disposed over the first sidewall spacers. The semiconductor device further includes a first protective layer formed over the first cap insulating layer, the first sidewall spacers and the second sidewall spacers. The first protective layer has a n-shape having a head portion and two leg portions in a cross section along a second direction perpendicular to the first direction.

公开(公告)号：US20220069199A1

公开(公告)日：2022-03-03

申请号：US17002098

申请日：2020-08-25

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chih-Fan Huang ,  Hsiang-Ku Shen ,  Liang-Wei Wang ,  Chen-Chiu Huang ,  Dian-Hau Chen ,  Yen-Ming Chen

IPC分类号： H01L43/02 ,  H01L27/22 ,  H01L43/12

摘要： Semiconductor device and methods of forming the same are provided. A semiconductor device according to one embodiment includes a dielectric layer including a top surface, a plurality of magneto-resistive memory cells disposed in the dielectric layer and including top electrodes, a first etch stop layer disposed over the dielectric layer, a common electrode extending through the first etch stop layer to be in direct contact with the top electrodes, and a second etch stop layer disposed on the first etch stop layer and the common electrode. Top surfaces of the top electrodes are coplanar with the top surface of the dielectric layer

公开(公告)号：US20210118783A1

公开(公告)日：2021-04-22

申请号：US16656617

申请日：2019-10-18

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Hsiang-Ku Shen ,  Chun-Li Lin ,  Dian-Hau Chen

IPC分类号： H01L23/498 ,  H01L23/532 ,  H01L21/02 ,  H01L21/48

摘要： Semiconductor devices and methods of forming the same are provided. In one embodiment, a semiconductor device includes a redistribution layer including a first conductive feature and a second conductive feature, a first contact feature disposed over and electrically coupled to the first conductive feature, a second contact feature disposed over and electrically coupled to the second conductive feature, and a passivation feature extending from between the first conductive feature and the second conductive feature between the first contact feature and the second contact feature. The passivation feature includes a dielectric feature and a dielectric layer. The dielectric layer is disposed on a planar top surface of the dielectric feature and a composition of the dielectric feature is different from a composition of the dielectric layer.

公开(公告)号：US10797048B2

公开(公告)日：2020-10-06

申请号：US15870649

申请日：2018-01-12

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Hsiang-Ku Shen ,  Chih Wei Lu ,  Janet Chen ,  Jeng-Ya David Yeh

IPC分类号： H01L21/768 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/51 ,  H01L29/49

摘要： In a method of manufacturing a semiconductor device, first and second gate structures are formed. The first (second) gate structure includes a first (second) gate electrode layer and first (second) sidewall spacers disposed on both side faces of the first (second) gate electrode layer. The first and second gate electrode layers are recessed and the first and second sidewall spacers are recessed, thereby forming a first space and a second space over the recessed first and second gate electrode layers and first and second sidewall spacers, respectively. First and second protective layers are formed in the first and second spaces, respectively. First and second etch-stop layers are formed on the first and second protective layers, respectively. A first depth of the first space above the first side wall spacers is different from a second depth of the first space above the first gate electrode layer.

公开(公告)号：US10056407B2

公开(公告)日：2018-08-21

申请号：US15061621

申请日：2016-03-04

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Hsiang-Ku Shen ,  Yu-Lien Huang ,  Wilson Huang ,  Janet Chen ,  Jeng-Ya David Yeh

IPC分类号： H01L21/84 ,  H01L27/12 ,  H01L29/66 ,  H01L29/417 ,  H01L29/49 ,  H01L21/768

CPC分类号： H01L27/1211 ,  H01L21/76829 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/845 ,  H01L29/41791 ,  H01L29/495 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/6656 ,  H01L29/66628

摘要： A semiconductor device includes a first gate structure disposed on a substrate. The first gate structure includes a first gate electrode, a first cap insulating layer disposed over the first gate electrode and first sidewall spacers disposed on both side faces of the first gate electrode and the first cap insulating layer. The semiconductor device further includes a first protective layer formed over the first cap insulating layer and at least one of the first sidewall spacers. The first protective layer includes at least one selected from the group consisting of AlON, AlN and amorphous silicon.

公开(公告)号：US09893062B2

公开(公告)日：2018-02-13

申请号：US15141476

申请日：2016-04-28

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Hsiang-Ku Shen ,  Chih Wei Lu ,  Janet Chen ,  Jeng-Ya David Yeh

IPC分类号： H01L21/02 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/3105 ,  H01L29/66 ,  H01L21/311 ,  H01L29/51 ,  H01L29/49

CPC分类号： H01L27/0886 ,  H01L21/02126 ,  H01L21/0214 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823475 ,  H01L23/485 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/517 ,  H01L29/66636

摘要： In a method of manufacturing a semiconductor device, first and second gate structures are formed. The first (second) gate structure includes a first (second) gate electrode layer and first (second) sidewall spacers disposed on both side faces of the first (second) gate electrode layer. The first and second gate electrode layers are recessed and the first and second sidewall spacers are recessed, thereby forming a first space and a second space over the recessed first and second gate electrode layers and first and second sidewall spacers, respectively. First and second protective layers are formed in the first and second spaces, respectively. First and second etch-stop layers are formed on the first and second protective layers, respectively. A first depth of the first space above the first side wall spacers is different from a second depth of the first space above the first gate electrode layer.

公开(公告)号：US12107041B2

公开(公告)日：2024-10-01

申请号：US18359011

申请日：2023-07-26

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yuan-Yang Hsiao ,  Hsiang-Ku Shen ,  Dian-Hau Chen ,  Hsiao Ching-Wen ,  Yao-Chun Chuang

IPC分类号： H01L23/522 ,  H01L21/768 ,  H01L23/528 ,  H01L49/02 ,  H10B12/00

CPC分类号： H01L23/5223 ,  H01L21/76843 ,  H01L23/528 ,  H01L28/40 ,  H01L28/75 ,  H01L28/84 ,  H01L28/91 ,  H10B12/033

摘要： A metal-insulator-metal (MIM) structure and methods of forming the same for reducing the accumulation of external stress at the corners of the conductor layers are disclosed herein. An exemplary device includes a substrate that includes an active semiconductor device. A stack of dielectric layers is disposed over the substrate. A lower contact is disposed over the stack of dielectric layers. A passivation layer is disposed over the lower contact. A MIM structure is disposed over the passivation layer, the MIM structure including a first conductor layer, a second conductor layer disposed over the first conductor layer, and a third conductor layer disposed over the second conductor layer. A first insulator layer is disposed between the first conductor layer and the second conductor layer. A second insulator layer is disposed between the second conductor layer and the third conductor layer. One or more corners of the third conductor layer are rounded.