公开(公告)号：US11664336B2

公开(公告)日：2023-05-30

申请号：US17522521

申请日：2021-11-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsien-Wei Chen ,  Jie Chen ,  Ming-Fa Chen

IPC: H01L23/00 ,  H01L23/48 ,  H01L23/532 ,  H01L21/768 ,  H01L21/18 ,  H01L33/00 ,  H01L23/373

CPC classification number: H01L24/09 ,  H01L21/187 ,  H01L21/76807 ,  H01L21/76871 ,  H01L23/481 ,  H01L23/53238 ,  H01L24/03 ,  H01L23/3735 ,  H01L33/0093 ,  H01L2224/02331 ,  H01L2224/02372 ,  H01L2924/01013

Abstract: A device includes an interconnect structure over a substrate, multiple first conductive pads over and connected to the interconnect structure, a planarization stop layer extending over the sidewalls and top surfaces of the first conductive pads of the multiple first conductive pads, a surface dielectric layer extending over the planarization stop layer, and multiple first bonding pads within the surface dielectric layer and connected to the multiple first conductive pads.

公开(公告)号：US11640958B2

公开(公告)日：2023-05-02

申请号：US17244133

申请日：2021-04-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsien-Wei Chen ,  Jie Chen

IPC: H01L25/00 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L23/498 ,  H01L21/48 ,  H01L21/683 ,  H01L25/065 ,  H01L25/10 ,  H01L25/18 ,  H01L21/304

Abstract: Embodiments of the present disclosure include semiconductor packages and methods of forming the same. An embodiment is a semiconductor package including a first package including one or more dies, and a redistribution layer coupled to the one or more dies at a first side of the first package with a first set of bonding joints. The redistribution layer including more than one metal layer disposed in more than one passivation layer, the first set of bonding joints being directly coupled to at least one of the one or more metal layers, and a first set of connectors coupled to a second side of the redistribution layer, the second side being opposite the first side.

公开(公告)号：US11482649B2

公开(公告)日：2022-10-25

申请号：US16941556

申请日：2020-07-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Fa Chen ,  Hsien-Wei Chen ,  Jie Chen

IPC: H01L33/52 ,  H01L33/62 ,  H01L25/16 ,  H01L31/0232 ,  H01L31/0203 ,  H01L31/18 ,  H01L33/58 ,  G02B6/42 ,  G02B6/12

Abstract: A semiconductor package includes a photonic die, an encapsulated electronic die, a substrate, and a lens structure. The photonic die includes an optical coupler. The encapsulated electronic die is disposed over and bonded to the photonic die. The encapsulated electronic die includes an electronic die and an encapsulating material at least laterally encapsulating the electronic die. The substrate is disposed over and bonded to the encapsulated electronic die. The lens structure is disposed over the photonic die and is overlapped with the optical coupler from a top view. The optical coupler is configured to be optically coupled to an optical signal source through the lens structure.

公开(公告)号：US20210327854A1

公开(公告)日：2021-10-21

申请号：US17361791

申请日：2021-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Shin-Puu Jeng ,  Der-Chyang Yeh ,  Hsien-Wei Chen ,  Jie Chen

IPC: H01L25/065 ,  H01L23/538 ,  H01L23/00 ,  H01L25/10 ,  H01L23/50 ,  H01L23/48

Abstract: A package includes a corner, a device die, a plurality of redistribution lines underlying the device die, and a plurality of metal pads electrically coupled to the plurality of redistribution lines. The plurality of metal pads includes a corner metal pad closest to the corner, wherein the corner metal pad is a center-facing pad having a bird-beak direction substantially pointing to a center of the package. The plurality of metal pads further includes a metal pad farther away from the corner than the corner metal pad, wherein the metal pad is a non-center-facing pad having a bird-beak direction pointing away from the center of the package.

公开(公告)号：US11121084B2

公开(公告)日：2021-09-14

申请号：US16526983

申请日：2019-07-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsien-Wei Chen ,  Ching-Jung Yang ,  Jie Chen ,  Ming-Fa Chen

IPC: H01L23/528 ,  H01L23/00 ,  H01L23/522 ,  H01L21/768 ,  H01L21/8234

Abstract: Integrated circuit devices and method of manufacturing the same are disclosed. An integrated circuit device includes an interconnect structure on a substrate, a passivation layer on the interconnect structure, a plurality of conductive pads on the passivation layer and a through interconnect via (TIV). The interconnect structure includes a plurality of dielectric layers and an interconnect in the plurality of dielectric layers. The plurality of conductive pads includes a first conductive pad electrically connecting the interconnect. The through interconnect via extends through the plurality of dielectric layers and electrically connecting a first conductive layer of the interconnect.

公开(公告)号：US11107680B2

公开(公告)日：2021-08-31

申请号：US15884328

申请日：2018-01-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jie Chen ,  Hsien-Wei Chen ,  Tzuan-Horng Liu ,  Ying-Ju Chen

IPC: H01L23/544 ,  G03F9/00 ,  H01L21/027 ,  H01L21/56 ,  H01L21/683 ,  H01L21/78 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00 ,  H01L21/66 ,  H01L25/065 ,  H01L25/10

Abstract: A first mask and a second mask are sequentially provided to perform a multi-step exposure and development processes. Through proper overlay design of the first mask and the second mask, conductive wirings having acceptable overlay offset are formed.

公开(公告)号：US11088041B2

公开(公告)日：2021-08-10

申请号：US16572612

申请日：2019-09-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsien-Wei Chen ,  Jie Chen ,  Ming-Fa Chen ,  Chih-Chia Hu

IPC: H01L23/34 ,  H01L23/48 ,  H01L21/4763 ,  H01L23/10 ,  H01L23/31 ,  H01L23/538 ,  H01L25/065 ,  H01L23/522

Abstract: Semiconductor packages are disclosed. A semiconductor package includes an integrated circuit, a first die and a second die. The first die includes a first bonding structure and a first seal ring. The first bonding structure is bonded to the integrated circuit and disposed at a first side of the first die. The second die includes a second bonding structure. The second bonding structure is bonded to the integrated circuit and disposed at a first side of the second die. The first side of the first die faces the first side of the second die. A first portion of the first seal ring is disposed between the first side and the first bonding structure, and a width of the first portion is smaller than a width of a second portion of the first seal ring.

公开(公告)号：US11018070B2

公开(公告)日：2021-05-25

申请号：US16547599

申请日：2019-08-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jie Chen ,  Hsien-Wei Chen ,  Ming-Fa Chen

IPC: H01L23/31 ,  H01L23/528 ,  H01L21/66 ,  H01L25/065 ,  H01L21/56 ,  H01L21/02 ,  H01L21/48 ,  H01L23/00

Abstract: A semiconductor die is provided. The semiconductor die includes a semiconductor substrate, an interconnection structure, conductive pads, a first passivation layer, and a second passivation layer. The interconnection structure is disposed on the semiconductor substrate. The conductive pads are disposed over and electrically connected to the interconnection structure. The first passivation layer and the second passivation layer are sequentially stacked on the conductive pads. The first passivation layer and the second passivation layer fill a gap between two adjacent conductive pads. The first passivation layer includes a first section and a second section. The first section extends substantially parallel to a top surface of the interconnection structure. The second section faces a side surface of one of the conductive pads. Thicknesses of the first section and the second section are different.

公开(公告)号：US20210134704A1

公开(公告)日：2021-05-06

申请号：US16856044

申请日：2020-04-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsien-Wei Chen ,  Jie Chen ,  Ming-Fa Chen ,  Sung-Feng Yeh

IPC: H01L23/48 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48

Abstract: A package structure including a first semiconductor die, a first insulating encapsulation, a bonding enhancement film, a second semiconductor die and a second insulating encapsulation is provided. The first insulating encapsulation laterally encapsulates a first portion of the first semiconductor die. The bonding enhancement film is disposed on a top surface of the first insulating encapsulation and laterally encapsulates a second portion of the first semiconductor die, wherein a top surface of the bonding enhancement film is substantially leveled with a top surface of the semiconductor die. The second semiconductor die is disposed on and bonded to the first semiconductor die and the bonding enhancement film. The second insulating encapsulation laterally encapsulates the second semiconductor die.

公开(公告)号：US20210091064A1

公开(公告)日：2021-03-25

申请号：US16882759

申请日：2020-05-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsien-Wei Chen ,  Jie Chen ,  Ming-Fa Chen

IPC: H01L25/00 ,  H01L21/56 ,  H01L23/00 ,  H01L25/065

Abstract: A method is provided. A bottom tier package structure is bonded to a support substrate through a first bonding structure, wherein the bottom tier package structure includes a first semiconductor die encapsulated by a first insulating encapsulation, and the first bonding structure includes stacked first dielectric layers and at least one stacked first conductive features penetrating through the stacked first dielectric layers. The support substrate is placed on a grounded stage such that the first semiconductor die is grounded through the at least one first stacked conductive features, the support substrate and the grounded stage. A second semiconductor die is bonded to the bottom tier package structure through a second bonding structure, wherein the second bonding structure includes stacked second dielectric layers and at least one stacked second conductive features penetrating through the stacked second dielectric layers. The second semiconductor die is encapsulated with a second insulating encapsulation.