公开(公告)号：US20240387743A1

公开(公告)日：2024-11-21

申请号：US18786796

申请日：2024-07-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuan-Lun Cheng ,  Yu-Xuan Huang ,  Hou-Yu Chen ,  Ching-Wei Tsai

IPC: H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  H01L23/528 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66

Abstract: Multigate devices and methods for fabricating such are disclosed herein. An exemplary multigate device includes a first FET disposed in a first region; and a second FET disposed in a second region of a substrate. The first FET includes first channel layers disposed over the substrate, and a first gate stack disposed on the first channel layers and extended to warp around each of the first channel layers. The second FET includes second channel layers disposed over the substrate, and a second gate stack disposed on the second channel layers and extended to warp around each of the second channel layers. A number of the first channel layers is greater than a number of the second channel layers. A bottommost one of the first channel layers is below a bottommost one of the second channel layers.

公开(公告)号：US20240379849A1

公开(公告)日：2024-11-14

申请号：US18783087

申请日：2024-07-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kai-Chieh Yang ,  Wei Ju Lee ,  Li-Yang Chuang ,  Pei-Yu Wang ,  Ching-Wei Tsai ,  Kuan-Lun Cheng

IPC: H01L29/78 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/08

Abstract: A semiconductor device and a method of forming the same are provided. A semiconductor device according to an embodiment includes a P-type field effect transistor (PFET) and an N-type field effect transistor (NFET). The PFET includes a first gate structure formed over a substrate, a first spacer disposed on a sidewall of the first gate structure, and an unstrained spacer disposed on a sidewall of the first spacer. The NET includes a second gate structure formed over the substrate, the first spacer disposed on a sidewall of the second gate structure, and a strained spacer disposed on a sidewall of the first spacer.

公开(公告)号：US20240379782A1

公开(公告)日：2024-11-14

申请号：US18780927

申请日：2024-07-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Wei Hsu ,  Lung-Kun Chu ,  Mao-Lin Huang ,  Jia-Ni Yu ,  Kuo-Cheng Chiang ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L29/417 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/786

Abstract: A semiconductor device includes a first interconnect structure and multiple channel layers stacked over the first interconnect structure. A bottommost one of the multiple channel layers is thinner than rest of the multiple channel layers. The semiconductor device further includes a gate stack wrapping around each of the channel layers except a bottommost one of the channel layers; a source/drain feature adjoining the channel layers; a first conductive via connecting the first interconnect structure to a bottom of the source/drain feature; and a dielectric feature under the bottommost one of the channel layers and directly contacting the first conductive via.

公开(公告)号：US20240363709A1

公开(公告)日：2024-10-31

申请号：US18770563

申请日：2024-07-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lin-Yu Huang ,  Li-Zhen Yu ,  Chia-Hao Chang ,  Cheng-Chi Chuang ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L29/417 ,  H01L21/768 ,  H01L23/522 ,  H01L29/08 ,  H01L29/78

CPC classification number: H01L29/41791 ,  H01L21/76877 ,  H01L23/5226 ,  H01L29/0847 ,  H01L29/785

Abstract: A semiconductor structure includes a substrate; a first structure over the substrate and having a first gate stack and two first gate spacers on two opposing sidewalls of the first gate stack; a second structure over the substrate and having a second gate stack and two second gate spacers on two opposing sidewalls of the second gate stack; a source/drain (S/D) feature over the substrate and adjacent to the first and the second gate stacks; an S/D contact over the S/D feature and between one of the first gate spacers and one of the second gate spacers; a conductive via disposed over and electrically connected to the S/D contact; and a dielectric liner layer. A first portion of the dielectric liner layer is disposed on a sidewall of the one of the first gate spacers and is directly above the S/D contact and spaced from the S/D contact.

公开(公告)号：US20240339545A1

公开(公告)日：2024-10-10

申请号：US18745704

申请日：2024-06-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ting Chung ,  Ching-Wei Tsai ,  Kuan-Lun Cheng

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/78696 ,  H01L29/0615 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66787 ,  H01L29/785

Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a fin substrate having a first dopant concentration; an anti-punch through (APT) layer disposed over the fin substrate, wherein the APT layer has a second dopant concentration that is greater than the first dopant concentration; a nanostructure including semiconductor layers disposed over the APT layer; a gate structure disposed over the nanostructure and wrapping each of the semiconductor layers, wherein the gate structure includes a gate dielectric and a gate electrode; a first epitaxial source/drain (S/D) feature and a second epitaxial S/D feature disposed over the APT layer, wherein the gate structure is disposed between the first epitaxial S/D feature and the second epitaxial S/D feature; and an isolation layer disposed between the APT layer and the fin substrate, wherein a material of the isolation layer is the same as a material of the gate dielectric.

公开(公告)号：US12107153B2

公开(公告)日：2024-10-01

申请号：US18298073

申请日：2023-04-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Cheng Ching ,  Shi-Ning Ju ,  Kuan-Ting Pan ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L29/66 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H10B10/00

CPC classification number: H01L29/6681 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/0653 ,  H10B10/12

Abstract: A first semiconductor fin is over the first region of the substrate and extends along a first direction. A second semiconductor fin is over the second region of the substrate and extends along the first direction. A dielectric structure is over the first region of the substrate and is in contact with a longitudinal end of the first semiconductor fin, wherein the dielectric structure is wider than the first semiconductor fin along a second direction perpendicular to the first direction. A first dielectric fin is over the second region of the substrate and is in contact with a longitudinal end of the second semiconductor fin, wherein the first dielectric fin and the second semiconductor fin have substantially a same width along the second direction.

公开(公告)号：US20240194764A1

公开(公告)日：2024-06-13

申请号：US18444918

申请日：2024-02-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Ching Wang ,  Jon-Hsu Ho ,  Wen-Hsing Hsieh ,  Kuan-Lun Cheng ,  Chung-Wei Wu ,  Zhiqiang Wu

IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/78

CPC classification number: H01L29/66484 ,  H01L21/823418 ,  H01L21/823431 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/7831 ,  H01L29/7848

Abstract: A semiconductor device includes semiconductor channel members disposed over a substrate, a gate dielectric layer disposed on and wrapping around the semiconductor channel members, a gate electrode layer disposed on the gate dielectric layer and wrapping around the semiconductor channel members, a source/drain (S/D) epitaxial layer in physical contact with the semiconductor channel members, and a dielectric spacer interposing the S/D epitaxial layer and the gate dielectric layer. The dielectric spacer includes a first dielectric layer in physical contact with the gate dielectric layer and a second dielectric layer in physical contact with the first dielectric layer. The first dielectric layer has a dielectric constant higher than that of the second dielectric layer. The second dielectric layer separates the first dielectric layer from physically contacting the S/D epitaxial layer.

公开(公告)号：US20240170553A1

公开(公告)日：2024-05-23

申请号：US18401764

申请日：2024-01-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ting Chung ,  Hou-Yu Chen ,  Kuan-Lun Cheng

IPC: H01L29/423 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/42392 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/7851

Abstract: A semiconductor device according to the present disclosure includes a stack of first channel layers, first and second source/drain (S/D) epitaxial features adjacent to opposite sides of at least a portion of the first channel layers, respectively, a stack of second channel layers stacked over the first channel layers, third and fourth S/D epitaxial features adjacent to opposite sides of at least a portion of the second channel layers, respectively, and a dielectric isolation layer disposed under the first and second S/D epitaxial features. A total active channel layer number of the first channel layers is different from a total active channel layer number of the second channel layers. The dielectric isolation layer is in physical contact with at least a bottommost one of the first channel layers.

公开(公告)号：US20240154043A1

公开(公告)日：2024-05-09

申请号：US18401769

申请日：2024-01-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Chiang ,  Shi Ning Ju ,  Guan-Lin Chen ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L29/786 ,  H01L21/02 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/78696 ,  H01L21/0262 ,  H01L29/401 ,  H01L29/42392 ,  H01L29/6653 ,  H01L29/66545

Abstract: A semiconductor device includes channel members vertically stacked, a gate structure wrapping around the channel members, a gate spacer disposed on sidewalls of the gate structure, an epitaxial feature abutting the channel members, and an inner spacer layer interposing the gate structure and the epitaxial feature. In a top view of the semiconductor device, the inner spacer layer has side portions in physical contact with the gate spacer and a middle portion stacked between the side portions. In a lengthwise direction of the channel members, the middle portion of the inner spacer layer is thicker than the side portions of the inner spacer layer.

公开(公告)号：US11949001B2

公开(公告)日：2024-04-02

申请号：US17699362

申请日：2022-03-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Ching Wang ,  Chung-I Yang ,  Jon-Hsu Ho ,  Wen-Hsing Hsieh ,  Kuan-Lun Cheng ,  Chung-Wei Wu ,  Zhiqiang Wu

IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/417 ,  H01L29/78

CPC classification number: H01L29/6681 ,  H01L21/823431 ,  H01L29/41791 ,  H01L29/785 ,  H01L2029/7858

Abstract: The present disclosure provides a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes channel members disposed over a substrate, a gate structure engaging the channel members, and an epitaxial feature adjacent the channel members. At least one of the channel members has an end portion in physical contact with an outer portion of the epitaxial feature. The end portion of the at least one of the channel members includes a first dopant of a first concentration. The outer portion of the epitaxial feature includes a second dopant of a second concentration. The first concentration is higher than the second concentration.