公开(公告)号：US20220285395A1

公开(公告)日：2022-09-08

申请号：US17333300

申请日：2021-05-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsu Ching Yang ,  Feng-Cheng Yang ,  Sheng-Chih Lai ,  Yu-Wei Jiang ,  Kuo-Chang Chiang ,  Hung-Chang Sun ,  Chen-Jun Wu ,  Chung-Te Lin

IPC: H01L27/11597 ,  H01L27/1159

Abstract: In some embodiments, the present disclosure relates to a method for forming a memory device, including forming a plurality of word line stacks respectively including a plurality of word lines alternatingly stacked with a plurality of insulating layers over a semiconductor substrate, forming a data storage layer along opposing sidewalls of the word line stacks, forming a channel layer along opposing sidewalls of the data storage layer, forming an inner insulating layer between inner sidewalls of the channel layer and including a first dielectric material, performing an isolation cut process including a first etching process through the inner insulating layer and the channel layer to form an isolation opening, forming an isolation structure filling the isolation opening and including a second dielectric material, performing a second etching process through the inner insulating layer on opposing sides of the isolation structure to form source/drain openings, and forming source/drain contacts in the source/drain openings.

公开(公告)号：US20210408044A1

公开(公告)日：2021-12-30

申请号：US17119346

申请日：2020-12-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Chang Chiang ,  Hung-Chang Sun ,  Sheng-Chih Lai ,  TsuChing Yang ,  Yu-Wei Jiang

IPC: H01L27/11597 ,  H01L27/11587 ,  H01L29/78 ,  H01L29/786 ,  G11C11/22

Abstract: A memory cell includes a thin film transistor over a semiconductor substrate. The thin film transistor includes a memory film contacting a word line; and an oxide semiconductor (OS) layer contacting a source line and a bit line, wherein the memory film is disposed between the OS layer and the word line; and a dielectric material separating the source line and the bit line. The dielectric material forms an interface with the OS layer. The dielectric material comprises hydrogen, and a hydrogen concentration at the interface between the dielectric material and the OS layer is no more than 3 atomic percent (at %).

公开(公告)号：US20250120091A1

公开(公告)日：2025-04-10

申请号：US18985411

申请日：2024-12-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Chang Chiang ,  Hung-Chang Sun ,  Sheng-Chih Lai ,  TsuChing Yang ,  Yu-Wei Jiang

IPC: H10B51/20 ,  H10B51/10 ,  H10D30/67

Abstract: A memory cell includes a thin film transistor over a semiconductor substrate, the thin film transistor including: a memory film contacting a word line; and an oxide semiconductor (OS) layer contacting a source line and a bit line, wherein the memory film is disposed between the OS layer and the word line, wherein the source line and the bit line each comprise a first conductive material touching the OS layer, and wherein the first conductive material has a work function less than 4.6. The memory cell further includes a dielectric material separating the source line and the bit line.

公开(公告)号：US11729987B2

公开(公告)日：2023-08-15

申请号：US17119409

申请日：2020-12-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Chang Chiang ,  Hung-Chang Sun ,  Sheng-Chih Lai ,  TsuChing Yang ,  Yu-Wei Jiang

IPC: H10B51/20 ,  H01L27/12 ,  H01L29/786 ,  H01L29/66 ,  G11C11/22

CPC classification number: H10B51/20 ,  G11C11/223 ,  H01L27/1225 ,  H01L29/66742 ,  H01L29/7869

Abstract: A memory cell includes a thin film transistor over a semiconductor substrate, the thin film transistor including: a memory film contacting a word line; and an oxide semiconductor (OS) layer contacting a source line and a bit line, wherein the memory film is disposed between the OS layer and the word line, wherein the source line and the bit line each comprise a first conductive material touching the OS layer, and wherein the first conductive material has a work function less than 4.6. The memory cell further includes a dielectric material separating the source line and the bit line.

公开(公告)号：US20230253464A1

公开(公告)日：2023-08-10

申请号：US18301113

申请日：2023-04-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Chang Chiang ,  Hung-Chang Sun ,  Sheng-Chih Lai ,  TsuChing Yang ,  Yu-Wei Jiang

IPC: H01L21/28 ,  G11C11/22 ,  H01L29/78 ,  H01L29/51 ,  H01L29/786

CPC classification number: H01L29/40111 ,  G11C11/223 ,  G11C11/2255 ,  H01L29/78391 ,  H01L29/516 ,  H01L29/7869 ,  G11C11/2257

Abstract: A memory cell includes a thin film transistor over a semiconductor substrate. The thin film transistor includes a memory film contacting a word line; and an oxide semiconductor (OS) layer contacting a source line and a bit line, wherein the memory film is disposed between the OS layer and the word line; and a dielectric material separating the source line and the bit line. The dielectric material forms an interface with the OS layer. The dielectric material comprises hydrogen, and a hydrogen concentration at the interface between the dielectric material and the OS layer is no more than 3 atomic percent (at %).

公开(公告)号：US11723199B2

公开(公告)日：2023-08-08

申请号：US17190735

申请日：2021-03-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsu Ching Yang ,  Sheng-Chih Lai ,  Yu-Wei Jiang ,  Kuo-Chang Chiang ,  Hung-Chang Sun ,  Chen-Jun Wu ,  Feng-Cheng Yang ,  Chung-Te Lin

IPC: H10B51/20 ,  H10B51/30 ,  H10B43/20 ,  H10B43/30

CPC classification number: H10B43/20 ,  H10B43/30 ,  H10B51/20 ,  H10B51/30

Abstract: A memory device includes a stack of gate electrode layers and interconnect layers arranged over a substrate. A first memory cell that is arranged over the substrate includes a first source/drain conductive lines and a second source/drain conductive line extending vertically through the stack of gate electrode layers. A channel layer and a memory layer are arranged on outer sidewalls of the first and second source/drain conductive lines. A first barrier structure is arranged between the first and second source/drain conductive lines. A first protective liner layer separates the first barrier structure from each of the first and second source/drain conductive lines. A second barrier structure is arranged on an opposite side of the first source/drain conductive line and is spaced apart from the first source/drain conductive line by a second protective liner layer.

公开(公告)号：US11640974B2

公开(公告)日：2023-05-02

申请号：US17119346

申请日：2020-12-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Chang Chiang ,  Hung-Chang Sun ,  Sheng-Chih Lai ,  Tsuching Yang ,  Yu-Wei Jiang

IPC: G11C11/22 ,  H01L21/28 ,  H01L29/786 ,  H01L29/78 ,  H01L29/51

Abstract: A memory cell includes a thin film transistor over a semiconductor substrate. The thin film transistor includes a memory film contacting a word line; and an oxide semiconductor (OS) layer contacting a source line and a bit line, wherein the memory film is disposed between the OS layer and the word line; and a dielectric material separating the source line and the bit line. The dielectric material forms an interface with the OS layer. The dielectric material comprises hydrogen, and a hydrogen concentration at the interface between the dielectric material and the OS layer is no more than 3 atomic percent (at %).

公开(公告)号：US20220285384A1

公开(公告)日：2022-09-08

申请号：US17190735

申请日：2021-03-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsu Ching Yang ,  Sheng-Chih Lai ,  Yu-Wei Jiang ,  Kuo-Chang Chiang ,  Hung-Chang Sun ,  Chen-Jun Wu ,  Feng-Cheng Yang ,  Chung-Te Lin

IPC: H01L27/11578 ,  H01L27/11568 ,  H01L27/1159 ,  H01L27/11597

Abstract: A memory device includes a stack of gate electrode layers and interconnect layers arranged over a substrate. A first memory cell that is arranged over the substrate includes a first source/drain conductive lines and a second source/drain conductive line extending vertically through the stack of gate electrode layers. A channel layer and a memory layer are arranged on outer sidewalls of the first and second source/drain conductive lines. A first barrier structure is arranged between the first and second source/drain conductive lines. A first protective liner layer separates the first barrier structure from each of the first and second source/drain conductive lines. A second barrier structure is arranged on an opposite side of the first source/drain conductive line and is spaced apart from the first source/drain conductive line by a second protective liner layer.