公开(公告)号：US10529593B2

公开(公告)日：2020-01-07

申请号：US15964092

申请日：2018-04-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Han Wang ,  Hung-Jui Kuo ,  Yu-Hsiang Hu

IPC: H01L21/56 ,  H01L23/31 ,  H01L23/367 ,  H01L23/04 ,  H01L25/00 ,  H01L21/48 ,  H01L25/065 ,  H01L23/498

Abstract: A semiconductor package manufacturing method thereof are provided. The semiconductor package includes a high-power device die, a redistribution structure, a heat dissipation module and a molding compound. The high-power device die has a front side and a back side opposite to the front side. The redistribution structure is disposed at the front side. The heat dissipation module is in direct contact with the back side. The molding compound is disposed between the redistribution structure and the heat dissipation module, and surrounding the high-power device die. The molding compound has a body portion and an extended portion. An interface between the body portion and the heat dissipation module is substantially parallel to the back side of the high-power device die. A thickness of the extended portion is greater than a thickness of the body portion.

公开(公告)号：US20190131235A1

公开(公告)日：2019-05-02

申请号：US15879457

申请日：2018-01-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Han Wang ,  Hung-Jui Kuo ,  Yu-Hsiang Hu

IPC: H01L23/522 ,  H01L21/66 ,  H01L21/56 ,  H01L21/78 ,  H01L23/31 ,  H01L21/768 ,  H01L23/00

Abstract: A stacked via structure including a first dielectric layer, a first conductive via, a first redistribution wiring, a second dielectric layer and a second conductive via is provided. The first dielectric layer includes a first via opening. The first conductive via is in the first via opening. A first level height offset is between a top surface of the first conductive via and a top surface of the first dielectric layer. The first redistribution wiring covers the top surface of the first conductive via and the top surface of the first dielectric layer. The second dielectric layer is disposed on the first dielectric layer and the first redistribution wiring. The second dielectric layer includes a second via opening. The second conductive via is in the second via opening. The second conductive via is electrically connected to the first redistribution wiring through the second via opening of the second dielectric layer.

公开(公告)号：US20250118609A1

公开(公告)日：2025-04-10

申请号：US18410301

申请日：2024-01-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin Chang ,  Po-Han Wang ,  Yu-Hsiang Hu ,  Hung-Jui Kuo

IPC: H01L23/31 ,  H01L23/00 ,  H01L23/498 ,  H01L23/522 ,  H01L25/00 ,  H01L25/065

Abstract: A method of forming a semiconductor package includes: surrounding a die with a molding material; and forming a redistribution structure (RDS) over the molding material and electrically coupled to the die, which includes: depositing a first dielectric layer over the molding material; patterning the first dielectric layer to form first openings in the first dielectric layer; performing a first descum process to clean the first openings; after performing the first descum process, forming a first redistribution layer (RDL) on the first dielectric layer; depositing a second dielectric layer over the molding material; patterning the second dielectric layer to form second openings in the second dielectric layer; performing a second descum process to clean the second openings, where the first and second descum processes are performed under different process conditions; and after performing the second descum process, forming a second RDL on the second dielectric layer.

公开(公告)号：US20230377969A1

公开(公告)日：2023-11-23

申请号：US18362083

申请日：2023-07-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Han Wang ,  Yu-Hsiang Hu ,  Hung-Jui Kuo

IPC: H01L21/768 ,  H01L23/00 ,  H01L23/48 ,  H01L23/522 ,  H01L23/528 ,  H01L23/31 ,  H01L21/56 ,  H01L23/532

CPC classification number: H01L21/76898 ,  H01L24/09 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/5283 ,  H01L21/76873 ,  H01L23/3171 ,  H01L21/563 ,  H01L23/5329 ,  H01L21/76885 ,  H01L2224/02373 ,  H01L2224/0231 ,  H01L2224/02379 ,  H01L2224/02381

Abstract: A method of fabricating a redistribution circuit structure including the following steps is provided. A conductive via is formed. A photosensitive dielectric layer is formed to cover the conductive via. The photosensitive dielectric layer is partially removed to reveal the conductive via at least through an exposure and development process. A redistribution wiring is formed on the photosensitive dielectric layer and the revealed conductive via.

公开(公告)号：US11682636B2

公开(公告)日：2023-06-20

申请号：US17215297

申请日：2021-03-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Han Wang ,  Yu-Hsiang Hu ,  Hung-Jui Kuo ,  Chen-Hua Yu

IPC: H01L23/58 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L23/485 ,  H01L23/00 ,  H01L21/683 ,  H01L25/10 ,  H01L25/00

CPC classification number: H01L23/585 ,  H01L21/4857 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/485 ,  H01L24/19 ,  H01L24/20 ,  H01L21/561 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68345 ,  H01L2221/68372 ,  H01L2221/68381 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1082 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/15311

Abstract: A method includes encapsulating a package component in an encapsulating material, with the encapsulating material including a portion directly over the package component. The portion of the encapsulating material is patterned to form an opening revealing a conductive feature in the package component. A redistribution line extends into the opening to contact the conductive feature. An electrical connector is formed over and electrically coupling to the conductive feature.

公开(公告)号：US11532540B2

公开(公告)日：2022-12-20

申请号：US16927020

申请日：2020-07-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Han Wang ,  Yu-Hsiang Hu ,  Hung-Jui Kuo ,  Chen-Hua Yu

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L23/522

Abstract: A method includes forming a buffer dielectric layer over a carrier, and forming a first dielectric layer and a first redistribution line over the buffer dielectric layer. The first redistribution line is in the first dielectric layer. The method further includes performing a planarization on the first dielectric layer to level a top surface of the first dielectric layer, forming a metal post over and electrically coupling to the first redistribution line, and encapsulating the metal post in an encapsulating material. The encapsulating material contacts a top surface of the planarized top surface of the first dielectric layer.

公开(公告)号：US11532531B2

公开(公告)日：2022-12-20

申请号：US16667854

申请日：2019-10-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Han Wang ,  Hung-Jui Kuo ,  Yu-Hsiang Hu ,  Sih-Hao Liao

IPC: H01L23/31 ,  H01L23/498 ,  H01L25/16 ,  H01L21/48 ,  H01L23/00 ,  H01L21/56

Abstract: A semiconductor package including a semiconductor die, an encapsulant, an electrical connector, a conductive pad and an inter-dielectric layer is provided. The encapsulant encapsulates the semiconductor die. The electrical connector is disposed over the semiconductor die. The conductive pad contacts the electrical connector and is disposed between the semiconductor die and the electrical connector. The inter-dielectric layer is disposed over the semiconductor die, wherein the inter-dielectric layer comprises an opening, and a portion of the opening is occupied by the conductive pad and the electrical connector.

公开(公告)号：US20220384333A1

公开(公告)日：2022-12-01

申请号：US17814995

申请日：2022-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yung-Chi Chu ,  Sih-Hao Liao ,  Po-Han Wang ,  Yu-Hsiang Hu ,  Hung-Jui Kuo

IPC: H01L23/522

Abstract: A device includes a sensor die having a sensing region at a top surface of the sensor die, an encapsulant at least laterally encapsulating the sensor die, a conductive via extending through the encapsulant, and a front-side redistribution structure on the encapsulant and on the top surface of the sensor die, wherein the front-side redistribution structure is connected to the conductive via and the sensor die, wherein an opening in the front-side redistribution structure exposes the sensing region of the sensor die, and wherein the front-side redistribution structure includes a first dielectric layer extending over the encapsulant and the top surface of the sensor die, a metallization pattern on the first dielectric layer, and a second dielectric layer extending over the metallization pattern and the first dielectric layer.

公开(公告)号：US11309265B2

公开(公告)日：2022-04-19

申请号：US16503773

申请日：2019-07-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Hsun Huang ,  Po-Han Wang ,  Ing-Ju Lee ,  Chao-Lung Chen ,  Cheng-Ming Wu

IPC: H01L23/00 ,  H01L23/532 ,  H01L23/528 ,  H01L21/768

Abstract: Methods of fabricating semiconductor devices are provided. The method includes providing a substrate and forming an interconnect structure on the substrate. The interconnect structure includes a top metal layer. The method also includes forming a first barrier film on the top metal layer using a first deposition process with a first level of power, and forming a second barrier film on the first barrier film using a second deposition process with a second level of power that is lower than the first level of power. The method further includes forming an aluminum-containing layer on the second barrier film. In addition, the method includes patterning the first barrier film, the second barrier film and the aluminum-containing layer to form a conductive pad structure.

公开(公告)号：US20210384075A1

公开(公告)日：2021-12-09

申请号：US17409010

申请日：2021-08-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Han Wang ,  Yu-Hsiang Hu ,  Hung-Jui Kuo

IPC: H01L21/768 ,  H01L23/00 ,  H01L23/48 ,  H01L23/522 ,  H01L23/528 ,  H01L23/31 ,  H01L21/56 ,  H01L23/532

Abstract: A method of fabricating a redistribution circuit structure including the following steps is provided. A conductive via is formed. A photosensitive dielectric layer is formed to cover the conductive via. The photosensitive dielectric layer is partially removed to reveal the conductive via at least through an exposure and development process. A redistribution wiring is formed on the photosensitive dielectric layer and the revealed conductive via.