公开(公告)号：US11856768B2

公开(公告)日：2023-12-26

申请号：US17750979

申请日：2022-05-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hsin-Wen Su ,  Chia-En Huang ,  Shih-Hao Lin ,  Lien-Jung Hung ,  Ping-Wei Wang

IPC: H10B41/30 ,  H01L23/522 ,  G11C7/18 ,  H01L29/872 ,  G11C8/14 ,  H10B43/30

CPC classification number: H10B41/30 ,  G11C7/18 ,  G11C8/14 ,  H01L23/5226 ,  H01L29/872 ,  H10B43/30

Abstract: A memory device includes a substrate, a first transistor and a second transistor, a Schottky diode, a first word line, a second word line, and a bit line. The first transistor and the second transistor are over the substrate, wherein a first source/drain structure of the first transistor is electrically connected to a first source/drain structure of the second transistor. The Schottky diode is electrically connected to a gate structure of the first transistor. The first word line is electrically connected to the gate structure of the first transistor through the Schottky diode. The second word line is electrically connected to a gate structure of the second transistor. The bit line is electrically connected to a second source/drain structure of the second transistor.

公开(公告)号：US20230326802A1

公开(公告)日：2023-10-12

申请号：US18329396

申请日：2023-06-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Szu-Chi Yang ,  Allen Chien ,  Tsai-Yu Huang ,  Chien-Chih Lin ,  Po-Kai Hsiao ,  Shih-Hao Lin ,  Chien-Chih Lee ,  Chih Chieh Yeh ,  Cheng-Ting Ding ,  Tsung-Hung Lee

IPC: H01L21/8234 ,  H01L29/06 ,  H01L29/10

CPC classification number: H01L21/823431 ,  H01L29/0607 ,  H01L21/823418 ,  H01L21/823412 ,  H01L29/1054

Abstract: The present disclosure provides methods of fabricating a semiconductor device. A method according to one embodiment includes forming, on a substrate, a first fin formed of a first semiconductor material and a second fin formed of a second semiconductor material different from the first semiconductor material, forming a semiconductor cap layer over the first fin and the second fin, and annealing the semiconductor cap layer at a first temperature while at least a portion of the semiconductor cap layer is exposed.

公开(公告)号：US20220352371A1

公开(公告)日：2022-11-03

申请号：US17811988

申请日：2022-07-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chuan Yang ,  Shih-Hao Lin

IPC: H01L29/78 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/165 ,  H01L29/267 ,  H01L29/10 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/311 ,  H01L27/092

Abstract: Nanostructure field-effect transistors (NSFETs) including isolation layers formed between epitaxial source/drain regions and semiconductor substrates and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a semiconductor substrate; a gate stack over the semiconductor substrate, the gate stack including a gate electrode and a gate dielectric layer; a first epitaxial source/drain region adjacent the gate stack; and a high-k dielectric layer extending between the semiconductor substrate and the first epitaxial source/drain region, the high-k dielectric layer contacting the first epitaxial source/drain region, the gate dielectric layer and the high-k dielectric layer including the same material.

公开(公告)号：US11482610B2

公开(公告)日：2022-10-25

申请号：US16931717

申请日：2020-07-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Hao Lin ,  Jui-Lin Chen ,  Hsin-Wen Su ,  Kian-Long Lim ,  Bwo-Ning Chen ,  Chih-Hsuan Chen

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/3115 ,  H01L21/02 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

Abstract: Methods of forming a semiconductor device are provided. A method according to the present disclosure includes forming, over a workpiece, a dummy gate stack comprising a first semiconductor material, depositing a first dielectric layer over the dummy gate stack using a first process, implanting the workpiece with a second semiconductor material different from the first semiconductor material, annealing the dummy gate stack after the implanting, and replacing the dummy gate stack with a metal gate stack.

公开(公告)号：US11342019B2

公开(公告)日：2022-05-24

申请号：US16937824

申请日：2020-07-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Hao Pao ,  Shih-Hao Lin ,  Kian-Long Lim

IPC: G11C11/418 ,  G11C11/419

Abstract: Memory systems are provided. In an embodiment, a memory device includes a word line driver coupled to a plurality of word lines, a recycle multiplexer coupled to a plurality of bit lines and a plurality of bit line bars, a memory cell array, and a compensation word line driver. The memory cell array includes a first end adjacent the word line driver, a second end away from the word line driver, and a plurality of memory cells. The compensation word line driver is disposed adjacent the second end of the memory cell array and coupled to the plurality of word lines. The recycle multiplexer is configured to selectively couple one or more of the plurality of bit lines or one or more of the plurality of bit line bars to the compensation word line driver.

公开(公告)号：US11043595B2

公开(公告)日：2021-06-22

申请号：US16441217

申请日：2019-06-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Wen Su ,  Yu-Kuan Lin ,  Chih-Chuan Yang ,  Chang-Ta Yang ,  Shih-Hao Lin

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/762

Abstract: A semiconductor device includes a memory macro having first and second well pick-up (WPU) areas along first and second edges of the memory macro, respectively, and memory bit areas between the first and the second WPU areas. The first and second WPU areas are oriented lengthwise generally along a first direction. In each of the first and second WPU areas, the memory macro includes n-type wells and p-type wells arranged alternately along the first direction with a well boundary between each of the n-type wells and the adjacent p-type well. The memory macro further includes active regions; an isolation structure; gate structures, and a first dielectric layer that is disposed at each of the well boundaries. From a top view, the first dielectric layer extends generally along a second direction perpendicular to the first direction and through all the gate structures in the first and the second WPU areas.

公开(公告)号：US20210098604A1

公开(公告)日：2021-04-01

申请号：US16931717

申请日：2020-07-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Hao Lin ,  Jui-Lin Chen ,  Hsin-Wen Su ,  Kian-Long Lim ,  Bwo-Ning Chen ,  Chih-Hsuan Chen

IPC: H01L29/66 ,  H01L21/3115 ,  H01L29/78

Abstract: Methods of forming a semiconductor device are provided. A method according to the present disclosure includes forming, over a workpiece, a dummy gate stack comprising a first semiconductor material, depositing a first dielectric layer over the dummy gate stack using a first process, implanting the workpiece with a second semiconductor material different from the first semiconductor material, annealing the dummy gate stack after the implanting, and replacing the dummy gate stack with a metal gate stack.

公开(公告)号：US20210098051A1

公开(公告)日：2021-04-01

申请号：US16937824

申请日：2020-07-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Hao Pao ,  Shih-Hao Lin ,  Kian-Long Lim

IPC: G11C11/418 ,  G11C11/419

Abstract: Memory systems are provided. In an embodiment, a memory device includes a word line driver coupled to a plurality of word lines, a recycle multiplexer coupled to a plurality of bit lines and a plurality of bit line bars, a memory cell array, and a compensation word line driver. The memory cell array includes a first end adjacent the word line driver, a second end away from the word line driver, and a plurality of memory cells. The compensation word line driver is disposed adjacent the second end of the memory cell array and coupled to the plurality of word lines. The recycle multiplexer is configured to selectively couple one or more of the plurality of bit lines or one or more of the plurality of bit line bars to the compensation word line driver.

公开(公告)号：US20210098049A1

公开(公告)日：2021-04-01

申请号：US16942278

申请日：2020-07-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chuan Yang ,  Shih-Hao Lin

IPC: G11C11/412 ,  G11C11/419 ,  H01L27/11 ,  H01L21/475

Abstract: Semiconductor devices and methods are provided. In an embodiment, a semiconductor device includes a bias source, a memory cell array including a first region adjacent to the bias source and a second region away from the bias source, and a conductive line electrically coupled to the bias source, a first memory cell in the first region and a second memory cell in the second region. The first memory cell is characterized by a first alpha ratio and the second memory cell is characterized by a second alpha ratio smaller than the first alpha ratio.

公开(公告)号：US12294030B2

公开(公告)日：2025-05-06

申请号：US18673746

申请日：2024-05-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Hao Lin ,  Chih-Hsuan Chen ,  Chia-Hao Pao ,  Chih-Chuan Yang ,  Chih-Yu Hsu ,  Hsin-Wen Su ,  Chia-Wei Chen

IPC: H01L29/786 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/167 ,  H01L29/45 ,  H01L29/66

Abstract: A semiconductor structure includes a first pair of source/drain features (S/D), a first stack of channel layers connected to the first pair of S/D, a second pair of S/D, and a second stack of channel layers connected to the second pair of S/D. The first pair of S/D each include a first epitaxial layer having a first dopant, a second epitaxial layer having a second dopant and disposed over the first epitaxial layer and connected to the first stack of channel layers, and a third epitaxial layer having a third dopant and disposed over the second epitaxial layer. The second pair of S/D each include a fourth epitaxial layer having a fourth dopant and connected to the second stack of channel layers, and a fifth epitaxial layer having a fifth dopant and disposed over the fourth epitaxial layer. The first dopant through the fourth dopant are of different species.