公开(公告)号：US09741831B2

公开(公告)日：2017-08-22

申请号：US15016214

申请日：2016-02-04

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wei-Yang Lee ,  Ting-Yeh Chen

IPC: H01L21/285 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/6681 ,  H01L21/2855 ,  H01L21/28556 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/7851

Abstract: A method for manufacturing a FinFET, and FinFETs are provided. In various embodiments, the method for manufacturing a FinFET includes forming a fin structure over a substrate. Next, a dummy gate is deposited across over the fin structure. The method continues with forming a pair of first spacers on sidewalls of the dummy gate. Then, a source/drain region is formed in the fin structure not covered by the dummy gate. The method further includes removing the dummy gate to expose the fin structure. After that, the first spacers are truncated, and a gate stack is formed to cover the exposed fin structure and top surfaces of the first spacers.

公开(公告)号：US09287403B1

公开(公告)日：2016-03-15

申请号：US14561472

申请日：2014-12-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wei-Yang Lee ,  Ting-Yeh Chen

IPC: H01L29/66 ,  H01L29/76 ,  H01L23/34 ,  H01L29/78 ,  H01L21/311

CPC classification number: H01L29/6681 ,  H01L21/2855 ,  H01L21/28556 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/7851

Abstract: A method for manufacturing a FinFET, and FinFETs are provided. In various embodiments, the method for manufacturing a FinFET includes forming a fin structure over a substrate. Next, a dummy gate is deposited across over the fin structure. The method continues with forming a pair of first spacers on sidewalls of the dummy gate. Then, a source/drain region is formed in the fin structure not covered by the dummy gate. The method further includes removing the dummy gate to expose the fin structure. After that, the first spacers are truncated, and a gate stack is formed to cover the exposed fin structure and top surfaces of the first spacers.

Abstract translation: 提供一种制造FinFET和FinFET的方法。 在各种实施例中，制造FinFET的方法包括在衬底上形成翅片结构。 接下来，跨越翅片结构沉积虚拟栅极。 该方法继续在伪栅极的侧壁上形成一对第一间隔物。 然后，在未被虚拟栅极覆盖的鳍结构中形成源极/漏极区域。 该方法还包括去除伪栅极以暴露翅片结构。 之后，第一间隔件被截断，并且形成一个栅叠层以覆盖暴露的散热片结构和第一间隔件的顶表面。

公开(公告)号：US11996467B2

公开(公告)日：2024-05-28

申请号：US18317319

申请日：2023-05-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzu-Hsiang Hsu ,  Ting-Yeh Chen ,  Wei-Yang Lee ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/764 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/165 ,  H01L29/78 ,  H10B10/00

CPC classification number: H01L29/66636 ,  H01L21/02507 ,  H01L21/02532 ,  H01L21/3065 ,  H01L21/764 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/7848 ,  H10B10/12 ,  H10B10/18

Abstract: A semiconductor device includes first and second semiconductor fins extending from a substrate and a source/drain region epitaxially grown in recesses of the first and second semiconductor fins. A top surface of the source/drain region is higher than a surface level with top surfaces of the first and second semiconductor fins. The source/drain region includes a plurality of buffer layers. Respective layers of the plurality of buffer layers are embedded between respective layers of the source/drain region.

公开(公告)号：US11688794B2

公开(公告)日：2023-06-27

申请号：US17651839

申请日：2022-02-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzu-Hsiang Hsu ,  Ting-Yeh Chen ,  Wei-Yang Lee ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC: H01L29/66 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/165 ,  H01L29/78 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/764 ,  H01L21/8238 ,  H10B10/00

CPC classification number: H01L29/66636 ,  H01L21/02507 ,  H01L21/02532 ,  H01L21/3065 ,  H01L21/764 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/7848 ,  H10B10/12 ,  H10B10/18

Abstract: A semiconductor device includes first and second semiconductor fins extending from a substrate and a source/drain region epitaxially grown in recesses of the first and second semiconductor fins. A top surface of the source/drain region is higher than a surface level with top surfaces of the first and second semiconductor fins. The source/drain region includes a plurality of buffer layers. Respective layers of the plurality of buffer layers are embedded between respective layers of the source/drain region.

公开(公告)号：US20220384660A1

公开(公告)日：2022-12-01

申请号：US17883234

申请日：2022-08-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ting-Yeh Chen ,  Wei-Yang Lee ,  Chia-Pin Lin

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66 ,  H01L21/02 ,  H01L21/285

Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises semiconductor layers over a substrate, wherein the semiconductor layers are stacked up and separated from each other, each semiconductor layer includes a first portion in a first channel region of the substrate and a second portion in a second channel region of the substrate, epitaxial layers formed in a source/drain region between the first channel region and the second channel region, wherein the epitaxial layers are separated from each other and each epitaxial layer is formed between the first portion and the second portion of each semiconductor layer, and a conductive feature wrapping each of the epitaxial layers.

公开(公告)号：US11107734B2

公开(公告)日：2021-08-31

申请号：US15830859

申请日：2017-12-04

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wei-Yang Lee ,  Feng-Cheng Yang ,  Ting-Yeh Chen

IPC: H01L21/8234 ,  H01L29/78 ,  H01L29/66 ,  H01L21/308 ,  H01L27/088 ,  H01L29/08

Abstract: A semiconductor device includes an isolation layer disposed over a substrate, first and second fin structures, a gate structure, a source/drain structure and a dielectric layer disposed on an upper surface of the isolation insulating layer. Both the first fin structure and the second fin structure are disposed over the substrate, and extend in a first direction in plan view. The gate structure is disposed over parts of the first and second fin structures, and extends in a second direction crossing the first direction. The first and second fin structures not covered by the gate structure are recessed below the upper surface of the isolation insulating layer. The source/drain structure is formed over the recessed first and second fin structures. A void is formed between the source/drain structure and the dielectric layer.

公开(公告)号：US20200251594A1

公开(公告)日：2020-08-06

申请号：US16853280

申请日：2020-04-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Yang Lee ,  Tzu-Hsiang Hsu ,  Ting-Yeh Chen ,  Feng-Cheng Yang

IPC: H01L29/78 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/11 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66

Abstract: A semiconductor structure includes a substrate, first fins extending from the substrate with a first fin pitch, and second fins extending from the substrate with a second fin pitch that is smaller than the first fin pitch. The semiconductor structure also includes first gate structures engaging the first fins, second gate structures engaging the second fins, first epitaxial semiconductor features adjacent the first gate structures, and second epitaxial semiconductor features adjacent the second gate structures. The first epitaxial semiconductor features are partially embedded in the first fins at a first depth, and the second epitaxial semiconductor features are partially embedded in the second fins at a second depth that is smaller than the first depth.

公开(公告)号：US10158017B2

公开(公告)日：2018-12-18

申请号：US15684088

申请日：2017-08-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Yang Lee ,  Tzu-Hsiang Hsu ,  Ting-Yeh Chen ,  Feng-Cheng Yang

IPC: H01L21/00 ,  H01L27/00 ,  H01L29/00 ,  H01L29/78 ,  H01L21/84 ,  H01L27/11 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66

Abstract: A semiconductor structure includes a substrate, first gate structures and second gate structures over the substrate, third epitaxial semiconductor features proximate the first gate structures, and fourth epitaxial semiconductor features proximate the second gate structures. The first gate structures have a greater pitch than the second gate structures. The third and fourth epitaxial semiconductor features are at least partially embedded in the substrate. A first proximity of the third epitaxial semiconductor features to the respective first gate structures is smaller than a second proximity of the fourth epitaxial semiconductor features to the respective second gate structures. In an embodiment, a first depth of the third epitaxial semiconductor features embedded into the substrate is greater than a second depth of the fourth epitaxial semiconductor features embedded into the substrate.

公开(公告)号：US09748389B1

公开(公告)日：2017-08-29

申请号：US15187976

申请日：2016-06-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Yang Lee ,  Tzu-Hsiang Hsu ,  Ting-Yeh Chen ,  Feng-Cheng Yang

IPC: H01L21/00 ,  H01L27/00 ,  H01L29/00 ,  H01L29/78 ,  H01L29/08 ,  H01L29/161 ,  H01L29/16 ,  H01L29/165 ,  H01L29/66 ,  H01L27/11 ,  H01L21/84

CPC classification number: H01L29/7848 ,  H01L21/845 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7851

Abstract: A method includes receiving a precursor having a substrate and first and second pluralities of gate structures, the first pluralities having a greater pitch than the second pluralities. The method further includes depositing a dielectric layer covering the substrate and the first and second pluralities; and performing an etching process to the dielectric layer. The etching process removes a first portion of the dielectric layer over the substrate, while a second portion of the dielectric layer remains over sidewalls of the first and second pluralities. The second portion of the dielectric layer is thicker over the sidewalls of the second plurality than over the sidewalls of the first plurality. The method further includes etching the substrate to form third and fourth pluralities of recesses adjacent the first and second pluralities, respectively; and epitaxially growing fifth and sixth pluralities of semiconductor features in the third and fourth pluralities, respectively.

公开(公告)号：US09570556B1

公开(公告)日：2017-02-14

申请号：US15060270

申请日：2016-03-03

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wei-Yang Lee ,  Feng-Cheng Yang ,  Ting-Yeh Chen

IPC: H01L31/0328 ,  H01L31/0336 ,  H01L31/072 ,  H01L31/109 ,  H01L29/08 ,  H01L29/24 ,  H01L29/267 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/762 ,  H01L29/0649 ,  H01L29/785 ,  Y02E10/50

Abstract: A semiconductor device includes an isolation layer disposed over a substrate, first and second fin structures, a gate structure, a source/drain structure. The first fin structure and the second fin structure are both disposed over the substrate, and extend in a first direction in plan view. The gate structure is disposed over parts of the first and second fin structures, and extends in a second direction crossing the first direction in plan view. A first void is formed in the source/drain structure, and a second void is formed in the source/drain structure and located above the first void.

Abstract translation: 半导体器件包括设置在衬底上的隔离层，第一和第二鳍结构，栅极结构，源极/漏极结构。 第一翅片结构和第二翅片结构均布置在基底上，并且在俯视图中沿第一方向延伸。 栅极结构设置在第一和第二鳍结构的一部分上，并且在平面图中沿与第一方向交叉的第二方向延伸。 在源极/漏极结构中形成第一空隙，并且在源极/漏极结构中形成第二空隙并且位于第一空隙之上。