公开(公告)号：US20200020794A1

公开(公告)日：2020-01-16

申请号：US16033256

申请日：2018-07-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Zhi-Chang LIN ,  Kai-Chieh YANG ,  Chia-Wei SU ,  Jia-Ni YU ,  Wei-Hao WU ,  Chih-Hao WANG

IPC: H01L29/78 ,  H01L21/8234 ,  H01L21/02 ,  H01L21/302 ,  H01L21/762 ,  H01L29/66 ,  H01L29/08 ,  H01L29/06 ,  H01L23/532

Abstract: A semiconductor device includes a substrate, a first fin, a second fin, a dummy fin, a first metal gate, a second metal gate, and an isolation structure. The first, the second and the dummy fins are on the substrate, and the dummy fin is disposed between the first fin and the second fin. The first metal gate and the second metal gate are over the first fin and the second fin, respectively. The isolation structure is on the dummy fin, and the dummy fin and the isolation structure separate the first metal gate and the second metal gate.

公开(公告)号：US20190139825A1

公开(公告)日：2019-05-09

申请号：US16222640

申请日：2018-12-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jia-Chuan YOU ,  Chia-Hao CHANG ,  Wei-Hao WU ,  Yu-Ming LIN ,  Chih-Hao WANG

IPC: H01L21/768 ,  H01L21/033 ,  H01L23/522 ,  H01L29/66 ,  H01L21/311 ,  H01L21/28

Abstract: A semiconductor device and a method for manufacturing a semiconductor device are provided. The semiconductor device includes a substrate, a gate stack, a gate spacer, a conductive feature, and a conductive cap. The substrate has a source/drain region. The gate stack is on the substrate. The gate spacer is alongside the gate stack. The conductive feature is on the source/drain region. The conductive cap is on the conductive feature and has a top in a position lower than a top of the gate spacer.

公开(公告)号：US20190088762A1

公开(公告)日：2019-03-21

申请号：US15706456

申请日：2017-09-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Huan-Chieh SU ,  Zhi-Chang LIN ,  Ting-Hung HSU ,  Jia-Ni YU ,  Wei-Hao WU ,  Chih-Hao WANG

IPC: H01L29/66 ,  H01L21/8234 ,  H01L27/088

CPC classification number: H01L29/66545 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/6681

Abstract: A method for manufacturing a semiconductor device is provided. The method for manufacturing a semiconductor device includes forming a gate electrode layer in a gate trench; filling a recess in the gate electrode layer with a dielectric feature; and etching back the gate electrode layer from top end surfaces of the gate electrode layer while leaving a portion of the gate electrode layer under the dielectric feature.

公开(公告)号：US20150194485A1

公开(公告)日：2015-07-09

申请号：US14661237

申请日：2015-03-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Mahaveer Sathaiya DHANYAKUMAR ,  Wei-Hao WU ,  Tsung-Hsing YU ,  Chia-Wen LIU ,  Tzer-Min SHEN ,  Ken-Ichi GOTO ,  Zhiqiang WU

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/167 ,  H01L29/78

CPC classification number: H01L29/0653 ,  H01L21/26586 ,  H01L21/76232 ,  H01L29/1033 ,  H01L29/1045 ,  H01L29/105 ,  H01L29/1095 ,  H01L29/167 ,  H01L29/66492 ,  H01L29/6659 ,  H01L29/66651 ,  H01L29/78 ,  H01L29/7833

Abstract: A MOSFET disposed between shallow trench isolation (STI) structures includes an epitaxial silicon layer formed over a substrate surface and extending over inwardly extending ledges of the STI structures. The gate width of the MOSFET is therefore the width of the epitaxial silicon layer and greater than the width of the original substrate surface between the STI structures. The epitaxial silicon layer is formed over the previously doped channel and is undoped upon deposition. A thermal activation operation may be used to drive dopant impurities into the transistor channel region occupied by the epitaxial silicon layer but the dopant concentration at the channel location where the epitaxial silicon layer intersects with the gate dielectric, is minimized.

Abstract translation: 设置在浅沟槽隔离（STI）结构之间的MOSFET包括形成在衬底表面上并在STI结构的向内延伸的突出部上延伸的外延硅层。 因此，MOSFET的栅极宽度是外延硅层的宽度，并且大于STI结构之间的原始衬底表面的宽度。 外延硅层形成在预先掺杂的沟道上，并且在沉积时未被掺杂。 可以使用热激活操作来将掺杂剂杂质驱动到由外延硅层占据的晶体管沟道区域中，但是外延硅层与栅极电介质相交的沟道位置处的掺杂剂浓度最小化。

公开(公告)号：US20200381299A1

公开(公告)日：2020-12-03

申请号：US16999997

申请日：2020-08-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jia-Chuan YOU ,  Chia-Hao CHANG ,  Wei-Hao WU ,  Yu-Ming LIN ,  Chih-Hao WANG

IPC: H01L21/768 ,  H01L29/66 ,  H01L21/28 ,  H01L21/311 ,  H01L23/522 ,  H01L21/033

Abstract: A semiconductor device includes a substrate, a gate stack, a first gate spacer and a second gate spacer, a first source/drain region and a second source/drain region, a first conductive feature and a second conductive feature, and a first contact plug and a second contact plug. The first conductive feature and the second conductive feature are over the first source/drain region and the second source/drain region, respectively. The first conductive cap and the second conductive cap are over the first conductive feature and the second conductive feature, respectively. The first contact plug and the second contact plug are over the first conductive cap and the second conductive cap, respectively, in which the first contact plug is separated from the first gate spacer, and the second contact plug is in contact with a sidewall and a top surface of the second gate spacer.

公开(公告)号：US20200303194A1

公开(公告)日：2020-09-24

申请号：US16895464

申请日：2020-06-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jia-Ni YU ,  Zhi-Chang LIN ,  Wei-Hao WU ,  Huan-Chieh SU ,  Chung-Wei HSU ,  Chih-Hao WANG

IPC: H01L21/28 ,  H01L21/762 ,  H01L29/40 ,  H01L29/66 ,  H01L21/768 ,  H01L29/78

Abstract: A FinFET device structure is provided. The FinFET device structure includes a substrate, a fin structure formed over the substrate, and an isolation structure formed over the substrate. The fin structure protrudes from the isolation structure. The FinFET device structure further includes a fin isolation structure formed over the isolation structure and a metal gate structure formed over the fin structure and the fin isolation structure.

公开(公告)号：US20190229201A1

公开(公告)日：2019-07-25

申请号：US16373988

申请日：2019-04-03

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wei-Hao WU ,  Zhi-Chang LIN ,  Ting-Hung HSU ,  Kuan-Lun CHENG

IPC: H01L29/423 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/762 ,  H01L27/12

Abstract: A method for manufacturing a semiconductor device includes forming a semiconductor strip over a substrate. The semiconductor strip includes a first semiconductor stack and a second semiconductor stack over the first semiconductor stack. A dummy gate stack is formed to cross the semiconductor strip. The dummy gate stack is replaced with a first metal gate stack and a second metal gate stack. The first metal gate stack is in contact with the first semiconductor layer of the first semiconductor stack and the second metal gate stack is in contact with the first semiconductor layer of the second semiconductor stack.

公开(公告)号：US20190165177A1

公开(公告)日：2019-05-30

申请号：US16176072

申请日：2018-10-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Liang CHEN ,  Chih-Ming LAI ,  Ching-Wei TSAI ,  Charles Chew-Yuen YOUNG ,  Jiann-Tyng TZENG ,  Kuo-Cheng CHING ,  Ru-Gun LIU ,  Wei-Hao WU ,  Yi-Hsiung LIN ,  Chia-Hao CHANG ,  Lei-Chun CHOU

IPC: H01L29/78 ,  H01L23/528 ,  H01L29/417 ,  H01L29/66 ,  H01L27/088

Abstract: The present disclosure describes various non-planar semiconductor devices, such as fin field-effect transistors (finFETs) to provide an example, having one or more metal rail conductors and various methods for fabricating these non-planar semiconductor devices. In some situations, the one or more metal rail conductors can be electrically connected to gate, source, and/or drain regions of these various non-planar semiconductor devices. In these situations, the one or more metal rail conductors can be utilized to electrically connect the gate, the source, and/or the drain regions of various non-planar semiconductor devices to other gate, source, and/or drain regions of various non-planar semiconductor devices and/or other semiconductor devices. However, in other situations, the one or more metal rail conductors can be isolated from the gate, the source, and/or the drain regions these various non-planar semiconductor devices. This isolation prevents electrical connection between the one or more metal rail conductors and the gate, the source, and/or the drain regions these various non-planar semiconductor devices.

公开(公告)号：US20190097011A1

公开(公告)日：2019-03-28

申请号：US15716699

申请日：2017-09-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wei-Hao WU ,  Zhi-Chang LIN ,  Ting-Hung HSU ,  Kuan-Lun CHENG

IPC: H01L29/423 ,  H01L21/762 ,  H01L29/66 ,  H01L21/8234 ,  H01L27/12

Abstract: A semiconductor device includes a substrate, a first device with a horizontal-gate-all-around configuration, and a second device with a horizontal-gate-all-around configuration. The first device is over the substrate. The second device is over the first device. A channel of the first device is between the substrate and a channel of the second device.