公开(公告)号：US10157895B2

公开(公告)日：2018-12-18

申请号：US15954772

申请日：2018-04-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Shin Chu ,  Kuan-Chieh Huang ,  Pao-Tung Chen ,  Shuang-Ji Tsai ,  Yi-Hao Chen ,  Feng-Kuei Chang

IPC: H01L21/768 ,  H01L23/52 ,  H01L23/528 ,  H01L25/065 ,  H01L21/311 ,  H01L23/31 ,  H01L23/48 ,  H01L23/522 ,  H01L23/58 ,  H01L23/00 ,  H01L25/00

Abstract: A three-dimensional (3D) integrated circuit (IC) die is provided. In some embodiments, a first IC die comprises a first semiconductor substrate, a first interconnect structure over the first semiconductor substrate, and a first hybrid bond (HB) structure over the first interconnect structure. The first HB structure comprises a HB link layer and a HB contact layer extending from the HB link layer to the first interconnect structure. A second IC die is over the first IC die, and comprises a second semiconductor substrate, a second HB structure, and a second interconnect structure between the second semiconductor substrate and the second HB structure. The second HB structure contacts the first HB structure. A seal-ring structure is in the first and second IC dies. Further, the seal-ring structure extends from the first semiconductor substrate to the second semiconductor substrate, and is defined in part by the HB contact layer.

公开(公告)号：US09972603B2

公开(公告)日：2018-05-15

申请号：US15383419

申请日：2016-12-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Shin Chu ,  Kuan-Chieh Huang ,  Pao-Tung Chen ,  Shuang-Ji Tsai ,  Yi-Hao Chen ,  Feng-Kuei Chang

IPC: H01L21/768 ,  H01L23/31 ,  H01L25/065 ,  H01L21/311 ,  H01L23/48 ,  H01L23/522 ,  H01L23/528 ,  H01L23/58 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L21/31111 ,  H01L21/76898 ,  H01L23/3171 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/585 ,  H01L24/19 ,  H01L24/24 ,  H01L24/82 ,  H01L25/50 ,  H01L2224/24145 ,  H01L2225/06541

Abstract: A three-dimensional (3D) integrated circuit (IC) die is provided. In some embodiments, a first IC die comprises a first semiconductor substrate, a first interconnect structure over the first semiconductor substrate, and a first hybrid bond (HB) structure over the first interconnect structure. The first HB structure comprises a HB link layer and a HB contact layer extending from the HB link layer to the first interconnect structure. A second IC die is over the first IC die, and comprises a second semiconductor substrate, a second HB structure, and a second interconnect structure between the second semiconductor substrate and the second HB structure. The second HB structure contacts the first HB structure. A seal-ring structure is in the first and second IC dies. Further, the seal-ring structure extends from the first semiconductor substrate to the second semiconductor substrate, and is defined in part by the HB contact layer.

公开(公告)号：US11289455B2

公开(公告)日：2022-03-29

申请号：US16898613

申请日：2020-06-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Min-Feng Kao ,  Dun-Nian Yaung ,  Hsing-Chih Lin ,  Jen-Cheng Liu ,  Yi-Shin Chu ,  Ping-Tzu Chen ,  Che-Wei Chen

IPC: H01L25/065 ,  H01L23/48 ,  H01L23/00 ,  H01L23/532 ,  H01L21/768

Abstract: In some embodiments, the present disclosure relates to a 3D integrated circuit (IC) stack that includes a first IC die bonded to a second IC die. The first IC die includes a first semiconductor substrate, a first interconnect structure arranged on a frontside of the first semiconductor substrate, and a first bonding structure arranged over the first interconnect structure. The second IC die includes a second semiconductor substrate, a second interconnect structure arranged on a frontside of the second semiconductor substrate, and a second bonding structure arranged on a backside of the second semiconductor substrate. The first bonding structure faces the second bonding structure. Further, the 3D IC stack includes a first backside contact that extends from the second bonding structure to the backside of the second semiconductor substrate and is thermally coupled to at least one of the first or second interconnect structures.

公开(公告)号：US20200027860A1

公开(公告)日：2020-01-23

申请号：US16584689

申请日：2019-09-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Shin Chu ,  Kuan-Chieh Huang ,  Pao-Tung Chen ,  Shuang-Ji Tsai ,  Yi-Hao Chen ,  Feng-Kuei Chang

IPC: H01L25/065 ,  H01L21/311 ,  H01L21/768 ,  H01L23/31 ,  H01L23/48 ,  H01L23/522 ,  H01L23/528 ,  H01L23/58 ,  H01L23/00 ,  H01L25/00

Abstract: A three-dimensional (3D) integrated circuit (IC) die is provided. In some embodiments, a first IC die comprises a first semiconductor substrate, a first interconnect structure over the first semiconductor substrate, and a first hybrid bond (HB) structure over the first interconnect structure. The first HB structure comprises a HB link layer and a HB contact layer extending from the HB link layer to the first interconnect structure. A second IC die is over the first IC die, and comprises a second semiconductor substrate, a second HB structure, and a second interconnect structure between the second semiconductor substrate and the second HB structure. The second HB structure contacts the first HB structure. A seal-ring structure is in the first and second IC dies. Further, the seal-ring structure extends from the first semiconductor substrate to the second semiconductor substrate, and is defined in part by the HB contact layer.

公开(公告)号：US20190109121A1

公开(公告)日：2019-04-11

申请号：US16216133

申请日：2018-12-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Shin Chu ,  Kuan-Chieh Huang ,  Pao-Tung Chen ,  Shuang-Ji Tsai ,  Yi-Hao Chen ,  Feng-Kuei Chang

IPC: H01L25/065 ,  H01L23/522 ,  H01L23/00 ,  H01L25/00 ,  H01L21/768 ,  H01L23/31 ,  H01L23/48 ,  H01L21/311 ,  H01L23/528 ,  H01L23/58

CPC classification number: H01L25/0657 ,  H01L21/31111 ,  H01L21/76898 ,  H01L23/3171 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/585 ,  H01L24/19 ,  H01L24/24 ,  H01L24/82 ,  H01L25/50 ,  H01L2224/24145 ,  H01L2225/06541

Abstract: A three-dimensional (3D) integrated circuit (IC) die is provided. In some embodiments, a first IC die comprises a first semiconductor substrate, a first interconnect structure over the first semiconductor substrate, and a first hybrid bond (HB) structure over the first interconnect structure. The first HB structure comprises a HB link layer and a HB contact layer extending from the HB link layer to the first interconnect structure. A second IC die is over the first IC die, and comprises a second semiconductor substrate, a second HB structure, and a second interconnect structure between the second semiconductor substrate and the second HB structure. The second HB structure contacts the first HB structure. A seal-ring structure is in the first and second IC dies. Further, the seal-ring structure extends from the first semiconductor substrate to the second semiconductor substrate, and is defined in part by the HB contact layer.

公开(公告)号：US20180233490A1

公开(公告)日：2018-08-16

申请号：US15954772

申请日：2018-04-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Shin Chu ,  Kuan-Chieh Huang ,  Pao-Tung Chen ,  Shuang-Ji Tsai ,  Yi-Hao Chen ,  Feng-Kuei Chang

IPC: H01L25/065 ,  H01L23/58 ,  H01L21/768 ,  H01L25/00 ,  H01L23/00 ,  H01L21/311 ,  H01L23/528 ,  H01L23/522 ,  H01L23/48 ,  H01L23/31

CPC classification number: H01L25/0657 ,  H01L21/31111 ,  H01L21/76898 ,  H01L23/3171 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/585 ,  H01L24/19 ,  H01L24/24 ,  H01L24/82 ,  H01L25/50 ,  H01L2224/24145 ,  H01L2225/06541

Abstract: A three-dimensional (3D) integrated circuit (IC) die is provided. In some embodiments, a first IC die comprises a first semiconductor substrate, a first interconnect structure over the first semiconductor substrate, and a first hybrid bond (HB) structure over the first interconnect structure. The first HB structure comprises a HB link layer and a HB contact layer extending from the HB link layer to the first interconnect structure. A second IC die is over the first IC die, and comprises a second semiconductor substrate, a second HB structure, and a second interconnect structure between the second semiconductor substrate and the second HB structure. The second HB structure contacts the first HB structure. A seal-ring structure is in the first and second IC dies. Further, the seal-ring structure extends from the first semiconductor substrate to the second semiconductor substrate, and is defined in part by the HB contact layer.

公开(公告)号：US20170186732A1

公开(公告)日：2017-06-29

申请号：US15383419

申请日：2016-12-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Shin Chu ,  Kuan-Chieh Huang ,  Pao-Tung Chen ,  Shuang-Ji Tsai ,  Yi-Hao Chen ,  Feng-Kuei Chang

IPC: H01L25/065 ,  H01L23/528 ,  H01L23/522 ,  H01L23/00 ,  H01L23/48 ,  H01L25/00 ,  H01L21/311 ,  H01L21/768 ,  H01L23/58 ,  H01L23/31

CPC classification number: H01L25/0657 ,  H01L21/31111 ,  H01L21/76898 ,  H01L23/3171 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/585 ,  H01L24/19 ,  H01L24/24 ,  H01L24/82 ,  H01L25/50 ,  H01L2224/24145 ,  H01L2225/06541

Abstract: A three-dimensional (3D) integrated circuit (IC) die is provided. In some embodiments, a first IC die comprises a first semiconductor substrate, a first interconnect structure over the first semiconductor substrate, and a first hybrid bond (HB) structure over the first interconnect structure. The first HB structure comprises a HB link layer and a HB contact layer extending from the HB link layer to the first interconnect structure. A second IC die is over the first IC die, and comprises a second semiconductor substrate, a second HB structure, and a second interconnect structure between the second semiconductor substrate and the second HB structure. The second HB structure contacts the first HB structure. A seal-ring structure is in the first and second IC dies. Further, the seal-ring structure extends from the first semiconductor substrate to the second semiconductor substrate, and is defined in part by the HB contact layer.

公开(公告)号：US12015099B2

公开(公告)日：2024-06-18

申请号：US17337265

申请日：2021-06-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yin-Kai Liao ,  Jen-Cheng Liu ,  Kuan-Chieh Huang ,  Chih-Ming Hung ,  Yi-Shin Chu ,  Hsiang-Lin Chen ,  Sin-Yi Jiang

IPC: H01L31/18 ,  H01L27/146 ,  H01L31/0288

CPC classification number: H01L31/1804 ,  H01L27/14643 ,  H01L27/14689 ,  H01L31/0288

Abstract: A method and structure providing an optical sensor having an optimized Ge—Si interface includes providing a substrate having a pixel region and a logic region. In some embodiments, the method further includes forming a trench within the pixel region. In various examples, and after forming the trench, the method further includes forming a doped semiconductor layer along sidewalls and along a bottom surface of the trench. In some embodiments, the method further includes forming a germanium layer within the trench and over the doped semiconductor layer. In some examples, and after forming the germanium layer, the method further includes forming an optical sensor within the germanium layer.

公开(公告)号：US11848345B2

公开(公告)日：2023-12-19

申请号：US17177696

申请日：2021-02-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsiang-Lin Chen ,  Yi-Shin Chu ,  Yin-Kai Liao ,  Sin-Yi Jiang ,  Kuan-Chieh Huang ,  Jhy-Jyi Sze

IPC: H01L27/146 ,  H01L31/105

CPC classification number: H01L27/14623 ,  H01L31/1055 ,  H01L27/14685

Abstract: Various embodiments of the present disclosure are directed towards an image sensor with a passivation layer for dark current reduction. A device layer overlies a substrate. Further, a cap layer overlies the device layer. The cap and device layers and the substrate are semiconductor materials, and the device layer has a smaller bandgap than the cap layer and the substrate. For example, the cap layer and the substrate may be silicon, whereas the device layer may be or comprise germanium. A photodetector is in the device and cap layers, and the passivation layer overlies the cap layer. The passivation layer comprises a high k dielectric material and induces formation of a dipole moment along a top surface of the cap layer.

公开(公告)号：US20210376086A1

公开(公告)日：2021-12-02

申请号：US17036287

申请日：2020-09-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yin-Kai Liao ,  Sin-Yi Jiang ,  Hsiang-Lin Chen ,  Yi-Shin Chu ,  Po-Chun Liu ,  Kuan-Chieh Huang ,  Jyh-Ming Hung ,  Jen-Cheng Liu

IPC: H01L29/10 ,  H01L29/66 ,  H01L29/167 ,  H01L29/49

Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a substrate having a first semiconductor material. A second semiconductor material is disposed on the first semiconductor material. The second semiconductor material is a group IV semiconductor or a group III-V compound semiconductor. A passivation layer is disposed on the second semiconductor material. The passivation layer includes the first semiconductor material. A first doped region and a second doped region extend through the passivation layer and into the second semiconductor material.