公开(公告)号：US11217585B2

公开(公告)日：2022-01-04

申请号：US16279824

申请日：2019-02-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Zhi-Chang Lin ,  Wei-Hao Wu ,  Jia-Ni Yu

IPC: H01L27/092 ,  H01L27/02 ,  H01L27/11 ,  H01L29/08 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/311

Abstract: A semiconductor device includes a first device fin and a second device fin that are each located in a first region of the semiconductor device. The first region has a first pattern density. A first dummy fin is located in the first region. The first dummy fin is disposed between the first device fin and the second device fin. The first dummy fin has a first height. A third device fin and a fourth device fin are each located in a second region of the semiconductor device. The second region has a second pattern density that is greater the first pattern density. A second dummy fin is located in the second region. The second dummy fin is disposed between the third device fin and the fourth device fin. The second dummy fin has a second height that is greater than the first height.

公开(公告)号：US11211293B2

公开(公告)日：2021-12-28

申请号：US16231613

申请日：2018-12-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Huan-Chieh Su ,  Chih-Hao Wang ,  Wei-Hao Wu ,  Zhi-Chang Lin ,  Jia-Ni Yu ,  Chung-Wei Hsu

IPC: H01L21/8234 ,  H01L21/762 ,  H01L29/66 ,  H01L27/088 ,  H01L29/78 ,  H01L21/308 ,  H01L29/423 ,  H01L21/768

Abstract: FinFET device and method of forming the same are provided. The method of forming the FinFET device includes the following steps. A substrate having a plurality of fins is provided. An isolation structure is on the substrate surrounding lower portions of the fins. A hybrid fin is formed aside the fins and on the isolation structure. A plurality of gate lines and a dielectric layer are formed. The gate lines are across the fins and the hybrid fin, the dielectric layer is aside the gate lines. A portion of the gate lines is removed, so as to form first trenches in the dielectric layer and in the gate lines, exposing a portion of the hybrid fin and a portion of the fins underlying the portion of the gate lines. The portion of the fins exposed by the first trench and the substrate underlying thereof are removed, so as to form a second trench under the first trench. An insulating structure is formed in the first trench and the second trench.

公开(公告)号：US11171053B2

公开(公告)日：2021-11-09

申请号：US16422559

申请日：2019-05-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Ching ,  Lin-Yu Huang ,  Huan-Chieh Su ,  Sheng-Tsung Wang ,  Zhi-Chang Lin ,  Jia-Chuan You ,  Chia-Hao Chang ,  Tien-Lu Lin ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L21/768 ,  H01L21/28 ,  H01L29/40 ,  H01L29/78

Abstract: A method of forming a semiconductor device includes providing a device having a gate stack including a metal gate layer. The device further includes a spacer layer disposed on a sidewall of the gate stack and a source/drain feature adjacent to the gate stack. The method further includes performing a first etch-back process to the metal gate layer to form an etched-back metal gate layer. In some embodiments, the method includes depositing a metal layer over the etched-back metal gate layer. In some cases, a semiconductor layer is formed over both the metal layer and the spacer layer to provide a T-shaped helmet layer over the gate stack and the spacer layer.

公开(公告)号：US20210343713A1

公开(公告)日：2021-11-04

申请号：US17170740

申请日：2021-02-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shi Ning Ju ,  Kuo-Cheng Chiang ,  Kuan-Ting Pan ,  Zhi-Chang Lin ,  Chih-Hao Wang ,  Shih-Cheng Chen

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/28 ,  H01L21/8238 ,  H01L29/66

Abstract: Self-aligned gate cutting techniques are disclosed herein that provide dielectric gate isolation fins for isolating gates of multigate devices from one another. An exemplary device includes a first multigate device having first source/drain features and a first metal gate that surrounds a first channel layer and a second multigate device having second source/drain features and a second metal gate that surrounds a second channel layer. A dielectric gate isolation fin separates the first metal gate from the second metal gate. The dielectric gate isolation fin includes a first dielectric layer having a first dielectric constant and a second dielectric layer having a second dielectric constant disposed over the first dielectric layer. The second dielectric constant is greater than the first dielectric constant. The first metal gate and the second metal gate physically contact the first channel layer and the second channel layer, respectively, and the dielectric gate isolation fin.

公开(公告)号：US11139379B2

公开(公告)日：2021-10-05

申请号：US16744459

申请日：2020-01-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Zhi-Chang Lin ,  Shih-Cheng Chen ,  Kuo-Cheng Chiang ,  Pei-Hsun Wang ,  Chih-Hao Wang

IPC: H01L29/417 ,  H01L29/06 ,  H01L29/423 ,  H01L29/40 ,  H01L21/8238

Abstract: A semiconductor structure is provided. The semiconductor structure includes nanostructures over a substrate, a gate stack around the nanostructures, a gate spacer layer alongside the gate stack, an inner spacer layer between the gate spacer layer and the nanostructures, a source/drain feature adjoining the nanostructures, a contact plug over the source/drain feature, and a silicon germanium layer along the surface of the source/drain feature and between the contact plug and the inner spacer layer.

公开(公告)号：US11133394B2

公开(公告)日：2021-09-28

申请号：US16373988

申请日：2019-04-03

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wei-Hao Wu ,  Zhi-Chang Lin ,  Ting-Hung Hsu ,  Kuan-Lun Cheng

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/786 ,  H01L27/092 ,  B82Y10/00 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/775 ,  H01L21/822 ,  H01L27/06 ,  H01L27/12 ,  H01L29/08 ,  H01L27/088

Abstract: A method for manufacturing a semiconductor device includes forming a semiconductor strip over a substrate. The semiconductor strip includes a first semiconductor stack and a second semiconductor stack over the first semiconductor stack. A dummy gate stack is formed to cross the semiconductor strip. The dummy gate stack is replaced with a first metal gate stack and a second metal gate stack. The first metal gate stack is in contact with the first semiconductor layer of the first semiconductor stack and the second metal gate stack is in contact with the first semiconductor layer of the second semiconductor stack.

公开(公告)号：US11107836B2

公开(公告)日：2021-08-31

申请号：US16571751

申请日：2019-09-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Zhi-Chang Lin ,  Chun-Hsiung Lin ,  Chih-Hao Wang

IPC: H01L29/66 ,  H01L27/12 ,  H01L21/308 ,  H01L29/06 ,  H01L29/78

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first gate stack over a substrate. The substrate has a base and a first fin structure over the base, and the first gate stack wraps around a first upper portion of the first fin structure. The method includes partially removing the first fin structure, which is not covered by the first gate stack. The method includes forming a first mask layer over a first sidewall of the first fin structure. The method includes forming a first stressor over a second sidewall of the first fin structure while the first mask layer covers the first sidewall. The first sidewall is opposite to the second sidewall. The method includes removing the first mask layer. The method includes forming a dielectric layer over the base and the first stressor. The dielectric layer covers the first sidewall.

公开(公告)号：US20210202719A1

公开(公告)日：2021-07-01

申请号：US17194967

申请日：2021-03-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Zhi-Chang Lin ,  Wei-Hao Wu ,  Jia-Ni Yu ,  Huan-Chieh Su ,  Ting-Hung Hsu ,  Chih-Hao Wang

IPC: H01L29/66 ,  H01L27/092 ,  H01L29/423 ,  H01L29/78 ,  H01L21/311 ,  H01L21/8238 ,  H01L21/768 ,  H01L21/8234

Abstract: A mask layer is formed over a semiconductor device. The semiconductor device includes: a gate structure, a first layer disposed over the gate structure, and an interlayer dielectric (ILD) disposed on sidewalls of the first layer. The mask layer includes an opening that exposes a portion of the first layer and a portion of the ILD. A first etching process is performed to etch the opening partially into the first layer and partially into the ILD. A liner layer is formed in the opening after the first etching process has been performed. A second etching process is performed after the liner layer has been formed. The second etching process extends the opening downwardly through the first layer and through the gate structure. The opening is filled with a second layer after the second etching process has been performed.

公开(公告)号：US20210126113A1

公开(公告)日：2021-04-29

申请号：US16872058

申请日：2020-05-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Zhi-Chang Lin ,  Shih-Cheng Chen ,  Lo-Heng Chang ,  Jung-Hung Chang ,  Kuo-Cheng Chiang

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/417 ,  H01L21/8234

Abstract: Semiconductor devices using a dielectric structure and methods of manufacturing are described herein. The semiconductor devices are directed towards gate-all-around (GAA) devices that are formed over a substrate and are isolated from one another by the dielectric structure. The dielectric structure is formed over the fin between two GAA devices and cuts a gate electrode that is formed over the fin into two separate gate electrodes. The two GAA devices are also formed with bottom spacers underlying source/drain regions of the GAA devices. The bottom spacers isolate the source/drain regions from the substrate. The dielectric structure is formed with a shallow bottom that is located above the bottoms of the bottom spacers.

公开(公告)号：US20210118748A1

公开(公告)日：2021-04-22

申请号：US17113431

申请日：2020-12-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsu-Hsiu Perng ,  Kai-Chieh Yang ,  Zhi-Chang Lin ,  Teng-Chun Tsai ,  Wei-Hao Wu

IPC: H01L21/8238 ,  H01L29/49 ,  H01L29/66 ,  C23C16/04 ,  H01L21/28 ,  H01L29/51 ,  H01L29/78

Abstract: A method includes forming a gate stack, which includes a gate dielectric and a metal gate electrode over the gate dielectric. An inter-layer dielectric is formed on opposite sides of the gate stack. The gate stack and the inter-layer dielectric are planarized. The method further includes forming an inhibitor film on the gate stack, with at least a portion of the inter-layer dielectric exposed, selectively depositing a dielectric hard mask on the inter-layer dielectric, with the inhibitor film preventing the dielectric hard mask from being formed thereon, and etching to remove a portion of the gate stack, with the dielectric hard mask acting as a portion of a corresponding etching mask.