公开(公告)号：US20160064560A1

公开(公告)日：2016-03-03

申请号：US14935760

申请日：2015-11-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsung-Hsing Yu ,  Chia-Wen Liu ,  Yeh Hsu ,  Shih-Syuan Huang ,  Ken-Ichi Goto ,  Zhiqiang Wu

IPC: H01L29/78 ,  H01L29/16 ,  H01L29/10 ,  H01L29/08

CPC classification number: H01L29/7836 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/30604 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/1083 ,  H01L29/16 ,  H01L29/161 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833

Abstract: The present disclosure relates to a transistor device having an epitaxial carbon layer and/or a carbon implantation region that provides for a low variation of voltage threshold, and an associated method of formation. In some embodiments, the transistor device has an epitaxial region arranged within a recess within a semiconductor substrate. The epitaxial region has a carbon doped silicon epitaxial layer and a silicon epitaxial layer disposed onto the carbon doped silicon epitaxial layer. A gate structure is arranged over the silicon epitaxial layer. The gate structure has a gate dielectric layer disposed onto the silicon epitaxial layer and a gate electrode layer disposed onto the gate dielectric layer. A source region and a drain region are arranged on opposing sides of a channel region disposed below the gate structure.

Abstract translation: 本发明涉及一种具有提供低电压阈值变化的外延碳层和/或碳注入区域的晶体管器件以及相关的形成方法。 在一些实施例中，晶体管器件具有布置在半导体衬底内的凹槽内的外延区域。 外延区域具有碳掺杂硅外延层和设置在掺碳硅外延层上的硅外延层。 栅极结构布置在硅外延层的上方。 栅极结构具有设置在硅外延层上的栅极介电层和设置在栅极介电层上的栅极电极层。 源极区域和漏极区域布置在设置在栅极结构下方的沟道区域的相对侧上。

公开(公告)号：US09236445B2

公开(公告)日：2016-01-12

申请号：US14156505

申请日：2014-01-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Wen Liu ,  Tsung-Hsing Yu ,  Wei-Hao Wu ,  Meikei Ieong ,  Ken-Ichi Goto ,  Zhiqiang Wu

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/36

CPC classification number: H01L29/66545 ,  H01L29/1083 ,  H01L29/36 ,  H01L29/66575 ,  H01L29/66621 ,  H01L29/66636 ,  H01L29/66651 ,  H01L29/78 ,  H01L29/7833

Abstract: The disclosure provides a method of forming a transistor. In this method, a dummy gate structure is formed over a semiconductor substrate. Source/drain regions are then formed in the semiconductor substrate such that a channel region, which is arranged under the dummy gate structure in the semiconductor substrate, separates the source/drains from one another. After the source/drain regions have been formed, the dummy gate structure is removed. After the dummy gate structure has been removed, a surface region of the channel region is removed to form a channel region recess. A replacement channel region is then epitaxially grown in the channel region recess.

Abstract translation: 本公开提供了一种形成晶体管的方法。 在该方法中，在半导体衬底上形成虚拟栅极结构。 然后在半导体衬底中形成源极/漏极区，使得布置在半导体衬底中的伪栅极结构下方的沟道区彼此分离源极/漏极。 在形成源极/漏极区之后，去除伪栅极结构。 在虚拟栅极结构被去除之后，去除沟道区域的表面区域以形成沟道区域凹陷。 然后在沟道区域凹陷中外延生长替换沟道区。

公开(公告)号：US20150200296A1

公开(公告)日：2015-07-16

申请号：US14156515

申请日：2014-01-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsung-Hsing Yu ,  Chia-Wen Liu ,  Yeh Hsu ,  Shih-Syuan Huang ,  Ken-Ichi Goto ,  Zhiqiang Wu

IPC: H01L29/78 ,  H01L21/306 ,  H01L29/16 ,  H01L21/02 ,  H01L29/08 ,  H01L29/66 ,  H01L21/265

CPC classification number: H01L29/7836 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/30604 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/1083 ,  H01L29/16 ,  H01L29/161 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833

Abstract: The present disclosure relates to a method of forming a transistor device having a carbon implantation region that provides for a low variation of voltage threshold, and an associated apparatus. The method is performed by forming a well region within a semiconductor substrate. The semiconductor substrate is selectively etched to form a recess within the well region. After formation of the recess, a carbon implantation is selectively performed to form a carbon implantation region within the semiconductor substrate at a position underlying the recess. An epitaxial growth is then performed to form one or more epitaxial layers within the recess at a position overlying the carbon implantation region. Source and drain regions are subsequently formed within the semiconductor substrate such that a channel region, comprising the one or more epitaxial layers, separates the source/drains from one another.

Abstract translation: 本公开涉及一种形成具有提供电压阈值的低变化的碳注入区域的晶体管器件的方法和相关联的器件。 该方法通过在半导体衬底内形成阱区进行。 选择性地蚀刻半导体衬底以在阱区内形成凹陷。 在形成凹部之后，选择性地进行碳注入，以在凹部下方的位置在半导体衬底内形成碳注入区域。 然后进行外延生长以在覆盖碳注入区域的位置处在凹槽内形成一个或多个外延层。 源极和漏极区域随后形成在半导体衬底内，使得包括一个或多个外延层的沟道区域将源极/漏极彼此分离。

公开(公告)号：US12237414B2

公开(公告)日：2025-02-25

申请号：US17314815

申请日：2021-05-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Ching Wang ,  Wen-Yuan Chen ,  Wen-Hsing Hsieh ,  Kuan-Lun Cheng ,  Chung-Wei Wu ,  Zhiqiang Wu

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/265 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: A method includes receiving a semiconductor substrate. The semiconductor substrate has a top surface and includes a semiconductor element. Moreover, the semiconductor substrate has a fin structure formed thereon. The method also includes recessing the fin structure to form source/drain trenches, forming a first dielectric layer over the recessed fin structure in the source/drain trenches, implanting a dopant element into a portion of the fin structure beneath a bottom surface of the source/drain trenches to form an amorphous semiconductor layer, forming a second dielectric layer over the recessed fin structure in the source/drain trenches, annealing the semiconductor substrate, and removing the first and second dielectric layers. After the annealing and the removing steps, the method further includes further recessing the recessed fin structure to provide a top surface. Additionally, the method includes forming an epitaxial layer from and on the top surface.

公开(公告)号：US12174545B2

公开(公告)日：2024-12-24

申请号：US18361254

申请日：2023-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tai-Yu Chen ,  Sagar Deepak Khivsara ,  Kuo-An Liu ,  Chieh Hsieh ,  Shang-Chieh Chien ,  Gwan-Sin Chang ,  Kai Tak Lam ,  Li-Jui Chen ,  Heng-Hsin Liu ,  Chung-Wei Wu ,  Zhiqiang Wu

IPC: G03F7/00

Abstract: A photolithography system utilizes tin droplets to generate extreme ultraviolet radiation for photolithography. The photolithography system irradiates the droplets with a laser. The droplets become a plasma and emit extreme ultraviolet radiation. The photolithography system senses contamination of a collector mirror by the tin droplets and adjusts the flow of a buffer fluid to reduce the contamination.

公开(公告)号：US12096544B2

公开(公告)日：2024-09-17

申请号：US18298927

申请日：2023-04-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tai-Yu Chen ,  Cho-Ying Lin ,  Sagar Deepak Khivsara ,  Hsiang Chen ,  Chieh Hsieh ,  Sheng-Kang Yu ,  Shang-Chieh Chien ,  Kai Tak Lam ,  Li-Jui Chen ,  Heng-Hsin Liu ,  Zhiqiang Wu

IPC: H05G2/00 ,  G03F7/00

CPC classification number: H05G2/008 ,  G03F7/70033 ,  G03F7/7055 ,  G03F7/7085 ,  H05G2/006

Abstract: A light source is provided capable of maintaining the temperature of a collector surface at or below a predetermined temperature. The light source in accordance with various embodiments of the present disclosure includes a processor, a droplet generator for generating a droplet to create extreme ultraviolet light, a collector for reflecting the extreme ultraviolet light into an intermediate focus point, a light generator for generating pre-pulse light and main pulse light, and a thermal image capture device for capturing a thermal image from a reflective surface of the collector.

公开(公告)号：US12009408B2

公开(公告)日：2024-06-11

申请号：US17870292

申请日：2022-07-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei Ju Lee ,  Chun-Fu Cheng ,  Chung-Wei Wu ,  Zhiqiang Wu

IPC: H01L29/08 ,  H01L21/02 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/66795 ,  H01L21/02236 ,  H01L21/02532 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823468 ,  H01L27/0886 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66636 ,  H01L29/7851 ,  H01L29/78696 ,  H01L29/0653 ,  H01L29/6656

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes channel members vertically stacked over a substrate, a gate structure engaging the channel members, a gate spacer layer disposed on sidewalls of the gate structure, an epitaxial feature abutting the channel members, an inner spacer layer interposing the gate structure and the epitaxial feature, and a semiconductor layer interposing the inner spacer layer and the epitaxial feature.

公开(公告)号：US20230387301A1

公开(公告)日：2023-11-30

申请号：US18447483

申请日：2023-08-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Ching Wang ,  Wen-Yuan Chen ,  Wen-Hsing Hsieh ,  Kuan-Lun Cheng ,  Chung-Wei Wu ,  Zhiqiang Wu

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  H01L21/02 ,  H01L21/265

CPC classification number: H01L29/7847 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/7848 ,  H01L29/78618 ,  H01L29/66742 ,  H01L21/0259 ,  H01L21/26526 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/78696

Abstract: A method includes receiving a semiconductor substrate. The semiconductor substrate has a top surface and includes a semiconductor element. Moreover, the semiconductor substrate has a fin structure formed thereon. The method also includes recessing the fin structure to form source/drain trenches, forming a first dielectric layer over the recessed fin structure in the source/drain trenches, implanting a dopant element into a portion of the fin structure beneath a bottom surface of the source/drain trenches to form an amorphous semiconductor layer, forming a second dielectric layer over the recessed fin structure in the source/drain trenches, annealing the semiconductor substrate, and removing the first and second dielectric layers. After the annealing and the removing steps, the method further includes further recessing the recessed fin structure to provide a top surface. Additionally, the method includes forming an epitaxial layer from and on the top surface.

公开(公告)号：US20230155008A1

公开(公告)日：2023-05-18

申请号：US18155392

申请日：2023-01-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Ching Wang ,  Chia-Ying Su ,  Wen-Hsing Hsieh ,  Kuan-Lun Cheng ,  Chung-Wei Wu ,  Zhiqiang Wu

IPC: H01L29/66 ,  H01L27/092 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L27/0924 ,  H01L21/823431 ,  H01L29/0669 ,  H01L29/7851

Abstract: Embodiments of the present disclosure includes a semiconductor device. The semiconductor device includes first suspended nanostructures vertically stacked over one another and disposed on a substrate, a first gate stack engaging the first suspended nanostructures, a first gate spacer disposed on sidewalls of the first gate stack, second suspended nanostructures vertically stacked over one another and disposed on the substrate, a second gate stack engaging the second suspended nanostructures, and a second gate spacer disposed on sidewalls of the second gate stack. A middle portion of the first suspended nanostructures has a first thickness measured in a direction perpendicular to a top surface of the substrate. A middle portion of the second suspended nanostructures has a second thickness measured in the direction. The second thickness is smaller than the first thickness.

公开(公告)号：US11489063B2

公开(公告)日：2022-11-01

申请号：US16931930

申请日：2020-07-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei Ju Lee ,  Chun-Fu Cheng ,  Chung-Wei Wu ,  Zhiqiang Wu

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/02 ,  H01L29/08 ,  H01L27/088 ,  H01L29/786 ,  H01L29/423 ,  H01L29/06

Abstract: The present disclosure provides a method of manufacturing a semiconductor device. The method includes forming a fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked; forming a sacrificial gate structure over the fin structure; etching a source/drain region of the fin structure, which is not covered by the sacrificial gate structure, thereby forming a source/drain trench; laterally etching the first semiconductor layers through the source/drain trench; forming an inner spacer layer, in the source/drain trench, at least on lateral ends of the etched first semiconductor layers; forming a seeding layer on the inner spacer layer; and growing a source/drain epitaxial layer in the source/drain trench, wherein the growing of the source/drain epitaxial layer includes growing the source/drain epitaxial layer from the seeding layer.