公开(公告)号：US11282779B2

公开(公告)日：2022-03-22

申请号：US16796905

申请日：2020-02-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kai-Chiang Wu ,  Jiun-Yi Wu ,  Yu-Min Liang

IPC: H01L23/498 ,  H01L23/00

Abstract: A package structure including a first circuit board structure, a redistribution layer structure, bonding elements, and a semiconductor package is provided. The redistribution layer structure is disposed over and electrically connected to the first circuit board structure. The bonding elements are disposed between and electrically connected to the redistribution layer structure and the first circuit board structure. Each of the bonding elements has a core portion and a shell portion surrounding the core portion. A stiffness of the core portion is higher than a stiffness of the shell portion. A semiconductor package is disposed over and electrically connected to the redistribution layer structure.

公开(公告)号：US11282761B2

公开(公告)日：2022-03-22

申请号：US16655264

申请日：2019-10-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jiun-Yi Wu ,  Chen-Hua Yu ,  Chung-Shi Liu ,  Yu-Min Liang

IPC: H01L23/29 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00

Abstract: Semiconductor packages and methods of forming the same are disclosed. One of the semiconductor packages includes a first redistribution layer structure, a package structure, a bus die and a plurality of connectors. The package structure is disposed over the first redistribution layer structure, and includes a plurality of package components. The bus die and the connectors are encapsulated by a first encapsulant between the package structure and the first redistribution layer structure. The bus die is electrically connected to two or more of the plurality of package components, and the package structure are electrically connected to the first redistribution layer structure through the plurality of connectors.

公开(公告)号：US11244879B2

公开(公告)日：2022-02-08

申请号：US16746976

申请日：2020-01-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chi-Yang Yu ,  Chien-Hsun Lee ,  Jung-Wei Cheng ,  Tsung-Ding Wang ,  Yu-Min Liang

IPC: H01L23/31 ,  H01L23/522

Abstract: A semiconductor package including a first semiconductor device, a second semiconductor device, an insulating encapsulant, a redistribution structure and a supporting element is provided. The insulating encapsulant encapsulates the first semiconductor device and the second semiconductor device. The redistribution structure is over the first semiconductor device, the second semiconductor device and the insulating encapsulant. The redistribution structure is electrically connected to the first semiconductor device and the second semiconductor device. The supporting element is embedded in one of the insulating encapsulant and the redistribution structure.

公开(公告)号：US20210242119A1

公开(公告)日：2021-08-05

申请号：US16916046

申请日：2020-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuan-Lin Ho ,  Chin-Liang Chen ,  Jiun-Yi Wu ,  Chi-Yang Yu ,  Yu-Min Liang ,  Wei-Yu Chen

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/683 ,  H01L21/48

Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a redistribution structure, a circuit substrate, and an insulating encapsulation. The redistribution structure includes a first under-bump metallization (UBM) pattern covered by a first dielectric layer, and the first UBM pattern includes a surface substantially leveled with a surface of the first dielectric layer. The circuit substrate is electrically coupled to the redistribution structure through a conductive joint disposed on the surface of the first UBM pattern. The insulating encapsulation is disposed on the redistribution structure to cover the circuit substrate.

公开(公告)号：US10957672B2

公开(公告)日：2021-03-23

申请号：US15835466

申请日：2017-12-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chi-Yang Yu ,  Chin-Liang Chen ,  Chien-Hsun Lee ,  Kuan-Lin Ho ,  Yu-Min Liang

IPC: H01L25/065 ,  H01L23/31 ,  H01L21/56 ,  H01L23/538 ,  H01L23/00 ,  H01L23/29 ,  H01L25/00 ,  H01L21/66

Abstract: A package structure and a method of forming the same are provided. The package structure includes a first die, a second die, a first encapsulant, a second encapsulant, and a plurality of conductive terminals. The first encapsulant is at least disposed between the first die and the second die, and on the second die. The second encapsulant is aside the first die and the second die. The conductive terminals are electrically connected to the first die and the second die through a redistribution layer (RDL) structure. An interface is existed between the first encapsulant and the second encapsulant.

公开(公告)号：US20200176346A1

公开(公告)日：2020-06-04

申请号：US16655264

申请日：2019-10-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jiun-Yi Wu ,  Chen-Hua Yu ,  Chung-Shi Liu ,  Yu-Min Liang

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/00

Abstract: Semiconductor packages and methods of forming the same are disclosed. One of the semiconductor packages includes a first redistribution layer structure, a package structure, a bus die and a plurality of connectors. The package structure is disposed over the first redistribution layer structure, and includes a plurality of package components. The bus die and the connectors are encapsulated by a first encapsulant between the package structure and the first redistribution layer structure. The bus die is electrically connected to two or more of the plurality of package components, and the package structure are electrically connected to the first redistribution layer structure through the plurality of connectors.

公开(公告)号：US20240234302A1

公开(公告)日：2024-07-11

申请号：US18617530

申请日：2024-03-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Shi Liu ,  Chien-Hsun Lee ,  Jiun Yi Wu ,  Hao-Cheng Hou ,  Hung-Jen Lin ,  Jung Wei Cheng ,  Tsung-Ding Wang ,  Yu-Min Liang ,  Li-Wei Chou

IPC: H01L23/522 ,  H01L21/56 ,  H01L21/683 ,  H01L21/768 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L23/5226 ,  H01L21/563 ,  H01L21/566 ,  H01L21/6835 ,  H01L21/76816 ,  H01L23/3157 ,  H01L23/49822 ,  H01L24/09 ,  H01L24/81 ,  H01L23/49816 ,  H01L24/13 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68381 ,  H01L2224/02331 ,  H01L2224/13101 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2924/18161

Abstract: An embodiment semiconductor package includes a bare semiconductor chip, a packaged semiconductor chip adjacent the bare semiconductor chip, and a redistribution structure bonded to the bare semiconductor chip and the packaged semiconductor chip. The redistribution structure includes a first redistribution layer having a first thickness; a second redistribution layer having a second thickness; and a third redistribution layer between the first redistribution layer and the second redistribution layer. The third redistribution layer has a third thickness greater than the first thickness and the second thickness. The package further includes an underfill disposed between the bare semiconductor chip and the redistribution structure and a molding compound encapsulating the bare semiconductor chip, the packaged semiconductor chip, and the underfill.

公开(公告)号：US20240136299A1

公开(公告)日：2024-04-25

申请号：US18401928

申请日：2024-01-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Yu Chen ,  Chun-Chih Chuang ,  Kuan-Lin Ho ,  Yu-Min Liang ,  Jiun Yi Wu

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/5389 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/19 ,  H01L24/20 ,  H01L2221/68372 ,  H01L2224/214 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/19106

Abstract: A package includes an interposer structure free of any active devices. The interposer structure includes an interconnect device; a dielectric film surrounding the interconnect device; and first metallization pattern bonded to the interconnect device. The package further includes a first device die bonded to an opposing side of the first metallization pattern as the interconnect device and a second device die bonded to a same side of the first metallization pattern as the first device die. The interconnect device electrically connects the first device die to the second device die.

公开(公告)号：US11515173B2

公开(公告)日：2022-11-29

申请号：US16869066

申请日：2020-05-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien-Hsun Chen ,  Yu-Min Liang ,  Yen-Ping Wang ,  Jiun Yi Wu ,  Chen-Hua Yu ,  Kai-Chiang Wu

IPC: H01L21/48 ,  H01L21/56 ,  H01L21/768 ,  H01L23/498 ,  H01L23/522 ,  H01L23/31 ,  H01L23/48

Abstract: Interconnect devices, packaged semiconductor devices and methods are disclosed herein that are directed towards embedding a local silicon interconnect (LSI) device and through substrate vias (TSVs) into system on integrated substrate (SoIS) technology with a compact package structure. The LSI device may be embedded into SoIS technology with through substrate via integration to provide die-to-die FL connection arrangement for super large integrated Fan-Out (InFO) for SBT technology in a SoIS device. Furthermore, the TSV connection layer may be formed using lithographic or photoresist-defined vias to provide eLSI P/G out to a ball-grid-array (BGA) connection interface.

公开(公告)号：US11508640B2

公开(公告)日：2022-11-22

申请号：US16874621

申请日：2020-05-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chi-Yang Yu ,  Chin-Liang Chen ,  Kuan-Lin Ho ,  Yu-Min Liang ,  Wen-Lin Chen

IPC: H01L23/373 ,  H01L23/00 ,  H01L23/31 ,  H01L23/495

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a first semiconductor die, a second semiconductor die, a molding compound, a heat dissipation module and an adhesive material. The first and second semiconductor dies are different types of dies and are disposed side by side. The molding compound encloses the first and second semiconductor dies. The heat dissipation module is located directly on and in contact with the back sides of the first and second semiconductor dies. The adhesive material is filled and contacted between the heat dissipation module and the molding compound. The semiconductor package has a central region and a peripheral region surrounding the central region. The first and second semiconductor dies are located within the central region. A sidewall of the heat dissipation module, a sidewall of the adhesive material and a sidewall of the molding compound are substantially coplanar.