公开(公告)号：US20210098302A1

公开(公告)日：2021-04-01

申请号：US16587013

申请日：2019-09-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shi Ning JU ,  Kuo-Cheng CHIANG ,  Ching-Wei TSAI ,  Kuan-Lun CHENG ,  Chih-Hao WANG

IPC: H01L21/8234 ,  H01L27/088 ,  H01L21/762 ,  H01L27/11 ,  H01L29/423

Abstract: A method of fabricating a device includes providing a first fin in a first device type region and a second fin in a second device type region. Each of the first and second fins include a plurality of semiconductor channel layers. A two-step recess of an STI region on opposing sides of each of the first and second fins is performed to expose a first number of semiconductor channel layers of the first fin and a second number of semiconductor channel layers of the second fin. A first gate structure is formed in the first device type region and a second gate structure is formed in the second device type region. The first gate structure is formed over the first fin having the first number of exposed semiconductor channel layers, and the second gate structure is formed over the second fin having the second number of exposed semiconductor channel layers.

公开(公告)号：US20210066291A1

公开(公告)日：2021-03-04

申请号：US16558010

申请日：2019-08-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yi-Hsiung LIN ,  Yi-Hsun CHIU ,  Shang-Wen CHANG ,  Ching-Wei TSAI ,  Yu-Xuan HUANG ,  Kuan-Lun CHENG ,  Chih-Hao WANG

IPC: H01L27/092 ,  H01L29/76 ,  H01L29/66 ,  H01L29/78

Abstract: The present disclosure relates to an integrated circuit. In one implementation, the integrated circuit may include a semiconductor substrate; at least one source region comprising a first doped semiconductor material; at least one drain region comprising a second doped semiconductor material; at least one gate formed between the at least one source region and the at least one drain region; and a nanosheet formed between the semiconductor substrate and the at least one gate. The nanosheet may be configured as a routing channel for the at least one gate and may have a first region having a first width and a second region having a second width. The first width may be smaller than the second width.

公开(公告)号：US20200328123A1

公开(公告)日：2020-10-15

申请号：US16911665

申请日：2020-06-25

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hsiao-Han LIU ,  Chih-Hao WANG ,  Kuo-Cheng CHIANG ,  Shi-Ning JU ,  Kuan-Lun CHENG

IPC: H01L21/8234 ,  H01L27/088

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a first fin structure, a second fin structure, a third fin structure, and a fourth fin structure formed over a substrate. The semiconductor structure further includes first nanostructures, second nanostructures, third nanostructures, and fourth nanostructures. The semiconductor structure further includes a first gate structure wrapping around the first nanostructures and the second nanostructures, and a second gate structure wrapping around the third nanostructures and the fourth nanostructures. In addition, a first lateral distance between the first fin structure and the second fin structure is shorter than a second lateral distance between the third fin structure and the fourth fin structure, and the first fin structure and the second fin structure are narrower than the third fin structure and the fourth fin structure.

公开(公告)号：US20200258999A1

公开(公告)日：2020-08-13

申请号：US16858891

申请日：2020-04-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Cheng CHING ,  Shi-Ning JU ,  Kuan-Ting PAN ,  Kuan-Lun CHENG ,  Chih-Hao WANG

IPC: H01L29/66 ,  H01L21/8234 ,  H01L21/308 ,  H01L29/78 ,  H01L29/161 ,  H01L29/16 ,  H01L29/08 ,  H01L29/06 ,  H01L21/8238 ,  H01L21/762 ,  H01L21/311

Abstract: Structures and formation methods of a semiconductor device structure are provided. The formation method includes forming a fin structure over a semiconductor substrate and forming a first isolation feature in the fin structure. The formation method also includes forming a second isolation feature over the semiconductor substrate after the formation of the first isolation feature. The fin structure and the first isolation feature protrude from the second isolation feature. The formation method further includes forming gate stacks over the second isolation feature, wherein the gate stacks surround the fin structure and the first isolation feature.

公开(公告)号：US20190334014A1

公开(公告)日：2019-10-31

申请号：US16504829

申请日：2019-07-08

Applicant: Taiwan Semiconductor Manufacturing, Co., Ltd.

Inventor： Kuo-Cheng CHING ,  Chih-Hao WANG ,  Kuan-Lun CHENG

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08

Abstract: Semiconductor structures including active fin structures, dummy fin structures, epitaxy layers, a Ge containing oxide layer and methods of manufacture thereof are described. By implementing the Ge containing oxide layer on the surface of the epitaxy layers formed on the source/drain regions of some of the FinFET devices, a self-aligned epitaxy process is enabled. By implementing dummy fin structures and a self-aligned etch, both the epitaxy layers and metal gate structures from adjacent FinFET devices are isolated in a self-aligned manner.

公开(公告)号：US20190165094A1

公开(公告)日：2019-05-30

申请号：US16053589

申请日：2018-08-02

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Cheng CHING ,  Ching-Wei TSAI ,  Kuan-Lun CHENG ,  Chih-Hao WANG

IPC: H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device includes a substrate, a semiconductor fin, an isolation plug, and an isolation structure. The semiconductor fin is over the substrate. The isolation plug is over the substrate and adjacent to an end of the semiconductor fin. The isolation structure is over the substrate and adjacent to sidewalls of the semiconductor fin and the isolation plug. A top surface of the isolation structure is in a position lower than a top surface of the isolation plug.

公开(公告)号：US20250142955A1

公开(公告)日：2025-05-01

申请号：US19010734

申请日：2025-01-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng CHING ,  Ching-Wei TSAI ,  Kuan-Lun CHENG ,  Chih-Hao WANG

IPC: H10D84/85 ,  H10D30/01 ,  H10D30/62

Abstract: A method for fabricating a semiconductor device includes providing a fin in a first region of a substrate. The fin includes a plurality of a first type of epitaxial layers and a plurality of a second type of epitaxial layers. A portion of a layer of the second type of epitaxial layers in a channel region of the first fin is removed to form a first gap between a first layer of the first type of epitaxial layers and a second layer of the first type of epitaxial layers. A first portion of a first gate structure is formed within the first gap and extending from a first surface of the first layer of the first type of epitaxial layers to a second surface of the second layer of the first type of epitaxial layers. A first source/drain feature is formed abutting the first portion of the first gate structure.

公开(公告)号：US20240387541A1

公开(公告)日：2024-11-21

申请号：US18789492

申请日：2024-07-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Wei HSU ,  Kuo-Cheng CHIANG ,  Mao-Lin HUANG ,  Lung-Kun CHU ,  Jia-Ni YU ,  Kuan-Lun CHENG ,  Chih-Hao WANG

IPC: H01L27/092 ,  H01L21/02 ,  H01L21/28 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/786

Abstract: A semiconductor device is provided. The semiconductor device includes first channel nanostructures in a first device region and second channel nanostructures in a second device region. The first channel nanostructures are disposed between first and second dielectric fins. The second channel nanostructures are disposed between first and third dielectric fins. A gate dielectric layer is formed to surround each of the first and the second channel nanostructures and over the first, the second and the third dielectric fins. A first work function layer is formed to surround each of the first channel nanostructures. A second work function layer is formed to surround each of the second channel nanostructures. A first gap is present between every adjacent first channel nanostructures and a second gap present is between every adjacent second channel nanostructures.

公开(公告)号：US20240222508A1

公开(公告)日：2024-07-04

申请号：US18438758

申请日：2024-02-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shi Ning JU ,  Kuo-Cheng CHIANG ,  Chih-Hao WANG ,  Kuan-Lun CHENG

IPC: H01L29/78 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/8238 ,  H01L23/522 ,  H01L23/528 ,  H01L27/088 ,  H01L27/092 ,  H01L29/417 ,  H01L29/66

CPC classification number: H01L29/7851 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823475 ,  H01L21/823871 ,  H01L21/823878 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/5286 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/4175 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/6681 ,  H01L21/76224 ,  H01L21/823418

Abstract: A semiconductor structure includes a power rail on a back side of the semiconductor structure, a first interconnect structure on a front side of the semiconductor structure, and a source feature, a drain feature, a first semiconductor fin, and a gate structure that are between the power rail and the first interconnect structure. The first semiconductor fin connects the source feature and the drain feature. The gate structure is disposed on a front surface and two side surfaces of the first semiconductor fin. The semiconductor structure further includes an isolation structure disposed between the power rail and the drain feature and between the power rail and the first semiconductor fin and a via penetrating through the isolation structure and connecting the source feature to the power rail.

公开(公告)号：US20230326986A1

公开(公告)日：2023-10-12

申请号：US18335741

申请日：2023-06-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lin-Yu HUANG ,  Li-Zhen YU ,  Chia-Hao CHANG ,  Cheng-Chi CHUANG ,  Kuan-Lun CHENG ,  Chih-Hao WANG

IPC: H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L21/28 ,  H01L21/8234

CPC classification number: H01L29/41775 ,  H01L29/4175 ,  H01L29/42376 ,  H01L29/6653 ,  H01L21/28114 ,  H01L21/823468 ,  H01L21/823475 ,  H01L29/517

Abstract: A semiconductor device includes a metal gate structure having sidewall spacers disposed on sidewalls of the metal gate structure. In some embodiments, a top surface of the metal gate structure is recessed with respect to a top surface of the sidewall spacers. The semiconductor device may further include a metal cap layer disposed over and in contact with the metal gate structure, where a first width of a bottom portion of the metal cap layer is greater than a second width of a top portion of the metal cap layer. In some embodiments, the semiconductor device may further include a dielectric material disposed on either side of the metal cap layer, where the sidewall spacers and a portion of the metal gate structure are disposed beneath the dielectric material.