公开(公告)号：US12068193B2

公开(公告)日：2024-08-20

申请号：US17377822

申请日：2021-07-16

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hsin-Yen Huang ,  Ting-Ya Lo ,  Shao-Kuan Lee ,  Chi-Lin Teng ,  Shau-Lin Shue ,  Hsiao-Kang Chang

IPC分类号： H01L21/768 ,  H01L23/532 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786

CPC分类号： H01L21/7682 ,  H01L21/7685 ,  H01L21/76877 ,  H01L23/5329 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/785 ,  H01L29/78696

摘要： A semiconductor device structure and method for forming the same are provided. The semiconductor device structure includes a first conductive layer formed over a substrate, and an air gap structure adjacent to the first conductive layer. The semiconductor device structure includes a support layer formed over the air gap structure. A bottom surface of the support layer is in direct contact with the air gap structure, and the bottom surface of the support layer is lower than a top surface of the first conductive layer and higher than a bottom surface of the first conductive layer.

公开(公告)号：US12002749B2

公开(公告)日：2024-06-04

申请号：US17412403

申请日：2021-08-26

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hsin-Yen Huang ,  Ting-Ya Lo ,  Shao-Kuan Lee ,  Chi-Lin Teng ,  Cheng-Chin Lee ,  Shau-Lin Shue ,  Hsiao-Kang Chang

IPC分类号： H01L23/522 ,  H01L21/768

CPC分类号： H01L23/5226 ,  H01L21/76831 ,  H01L21/76832

摘要： Some embodiments of the present disclosure relate to an integrated chip, including a semiconductor substrate and a dielectric layer disposed over the semiconductor substrate. A pair of metal lines are disposed over the dielectric layer and laterally spaced apart from one another by a cavity. A barrier layer structure extends along nearest neighboring sidewalls of the pair of metal lines such that the cavity is defined by inner sidewalls of the barrier layer structure and a top surface of the dielectric layer.

公开(公告)号：US20240088025A1

公开(公告)日：2024-03-14

申请号：US18519516

申请日：2023-11-27

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hsin-Yen Huang ,  Kai-Fang Cheng ,  Chi-Lin Teng ,  Hai-Ching Chen ,  Tien-I Bao

IPC分类号： H01L23/522 ,  H01L21/02 ,  H01L21/311 ,  H01L21/768 ,  H01L23/532

CPC分类号： H01L23/5226 ,  H01L21/02178 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/31111 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76849 ,  H01L23/5329 ,  H01L23/53295 ,  H01L21/76807 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L2924/0002

摘要： The present disclosure provides a method for forming an integrated circuit (IC) structure. The method comprises providing a substrate including a conductive feature; forming aluminum (Al)-containing dielectric layer on the conductive feature; forming a low-k dielectric layer on the Al-containing dielectric layer; and etching the low-k dielectric layer to form a contact trench aligned with the conductive feature. A bottom of the contact trench is on a surface of the Al-containing dielectric layer.

公开(公告)号：US11923243B2

公开(公告)日：2024-03-05

申请号：US17460628

申请日：2021-08-30

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Hsin-Yen Huang ,  Ting-Ya Lo ,  Shao-Kuan Lee ,  Chi-Lin Teng ,  Cheng-Chin Lee ,  Shau-Lin Shue ,  Hsiao-Kang Chang

IPC分类号： H01L21/768 ,  H01L21/02 ,  H01L21/306

CPC分类号： H01L21/7682 ,  H01L21/76831 ,  H01L21/76865 ,  H01L21/76877 ,  H01L21/02167 ,  H01L21/30617

摘要： A method for manufacturing a semiconductor structure includes preparing a dielectric structure formed with trenches respectively defined by lateral surfaces of the dielectric structure, forming spacer layers on the lateral surfaces, filling an electrically conductive material into the trenches to form electrically conductive features, selectively depositing a blocking layer on the dielectric structure, selectively depositing a dielectric material on the electrically conductive features to form a capping layer, removing the blocking layer and the dielectric structure to form recesses, forming sacrificial features in the recesses, forming a sustaining layer to cover the sacrificial features; and removing the sacrificial features to obtain the semiconductor structure formed with air gaps confined by the sustaining layer and the spacer layers.

公开(公告)号：US20230377954A1

公开(公告)日：2023-11-23

申请号：US18363865

申请日：2023-08-02

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hsin-Yen Huang ,  Chi-Lin Teng ,  Hai-Ching Chen ,  Shau-Lin Shue ,  Shao-Kuan Lee ,  Cheng-Chin Lee ,  Ting-Ya Lo

IPC分类号： H01L21/768 ,  H01L23/532

CPC分类号： H01L21/7682 ,  H01L23/5329 ,  H01L23/528

摘要： Some embodiments relate to a semiconductor structure including a conductive wire disposed within a first dielectric structure. An etch stop layer overlies the first dielectric structure. A dielectric capping layer is disposed between an upper surface of the conductive wire and the etch stop layer. An upper dielectric layer is disposed along sidewalls of the conductive wire and an upper surface of the etch stop layer. The upper dielectric layer contacts an upper surface of the dielectric capping layer and has a top surface vertically above the etch stop layer.

公开(公告)号：US20230253286A1

公开(公告)日：2023-08-10

申请号：US18302210

申请日：2023-04-18

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shao-Kuan Lee ,  Cherng-Shiaw Tsai ,  Ting-Ya Lo ,  Cheng-Chin Lee ,  Chi-Lin Teng ,  Kai-Fang Cheng ,  Hsin-Yen Huang ,  Hsiao-Kang Chang ,  Shau-Lin Shue

IPC分类号： H01L23/373 ,  H01L21/768 ,  H01L23/48 ,  H01L23/532

CPC分类号： H01L23/373 ,  H01L21/7682 ,  H01L21/76877 ,  H01L23/481 ,  H01L23/53295

摘要： In some embodiments, the present disclosure relates to an integrated chip that includes an electrical interconnect structure, a thermal interconnect structure, and a thermal passivation layer over a substrate. The electrical interconnect structure includes interconnect vias and interconnect wires embedded within interconnect dielectric layers. The thermal interconnect structure is arranged beside the electrical interconnect structure and includes thermal vias, thermal wires, and/or thermal layers. Further, the thermal interconnect structure is embedded within the interconnect dielectric layers. The thermal passivation layer is arranged over a topmost one of the interconnect dielectric layers. The thermal interconnect structure has a higher thermal conductivity than the interconnect dielectric layers.

公开(公告)号：US20230068892A1

公开(公告)日：2023-03-02

申请号：US17412403

申请日：2021-08-26

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hsin-Yen Huang ,  Ting-Ya Lo ,  Shao-Kuan Lee ,  Chi-Lin Teng ,  Cheng-Chin Lee ,  Shau-Lin Shue ,  Hsiao-Kang Chang

IPC分类号： H01L23/522 ,  H01L21/768

摘要： Some embodiments of the present disclosure relate to an integrated chip, including a semiconductor substrate and a dielectric layer disposed over the semiconductor substrate. A pair of metal lines are disposed over the dielectric layer and laterally spaced apart from one another by a cavity. A barrier layer structure extends along nearest neighboring sidewalls of the pair of metal lines such that the cavity is defined by inner sidewalls of the barrier layer structure and a top surface of the dielectric layer.

公开(公告)号：US20220293512A1

公开(公告)日：2022-09-15

申请号：US17829590

申请日：2022-06-01

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Ting-Ya Lo ,  Chi-Lin Teng ,  Hai-Ching Chen ,  Hsin-Yen Huang ,  Shau-Lin Shue ,  Shao-Kuan Lee ,  Cheng-Chin Lee

IPC分类号： H01L23/522 ,  H01L21/768 ,  H01L23/538

摘要： Some embodiments relate to a method for forming an integrated chip, the method includes forming a first conductive wire and a second conductive wire over a substrate. A dielectric structure is formed laterally between the first conductive wire and the second conductive wire. The dielectric structure comprises a first dielectric liner, a dielectric layer disposed between opposing sidewalls of the first dielectric liner, and a void between an upper surface of the first dielectric liner and a lower surface of the dielectric layer. A dielectric capping layer is formed along an upper surface of the dielectric structure. Sidewalls of the dielectric capping layer are aligned with sidewalls of the dielectric structure.

公开(公告)号：US20240274524A1

公开(公告)日：2024-08-15

申请号：US18635093

申请日：2024-04-15

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Ting-Ya Lo ,  Chi-Lin Teng ,  Hai-Ching Chen ,  Hsin-Yen Huang ,  Shau-Lin Shue ,  Shao-Kuan Lee ,  Cheng-Chin Lee

IPC分类号： H01L23/522 ,  H01L21/768 ,  H01L23/538

CPC分类号： H01L23/5222 ,  H01L21/76802 ,  H01L21/76831 ,  H01L23/5384 ,  H01L23/5386

摘要： Some embodiments relate to an integrated chip comprising a first conductive structure and a second conductive structure over a substrate. A first liner layer extends along sidewalls of the first and second conductive structure. A first dielectric layer is between opposing sidewalls of the first liner layer. An air-gap is disposed between a surface of the first liner layer and a surface of the first dielectric layer.

公开(公告)号：US12062572B2

公开(公告)日：2024-08-13

申请号：US17674064

申请日：2022-02-17

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Cheng-Chin Lee ,  Ting-Ya Lo ,  Chi-Lin Teng ,  Cherng-Shiaw Tsai ,  Shao-Kuan Lee ,  Kuang-Wei Yang ,  Gary Liu ,  Hsin-Yen Huang ,  Hsiao-Kang Chang ,  Shau-Lin Shue

IPC分类号： H01L21/768 ,  H01L23/532 ,  H01L23/522

CPC分类号： H01L21/7682 ,  H01L23/5329 ,  H01L23/5226 ,  H01L23/53295

摘要： A method for manufacturing a semiconductor device includes: forming a first feature and a second feature extending in a normal direction transverse to a substrate; directionally depositing a dielectric material upon the features at an inclined angle relative to the normal direction so as to form a cap layer including a top portion disposed on a top surface of each of the features, and two opposite wall portions extending downwardly from two opposite ends of the top portion to partially cover two opposite lateral surfaces of each of the features, respectively, the cap layer on the first feature being spaced apart from the cap layer on the second feature; forming a sacrificial feature in a recess between the features; forming a sustaining layer to cover the sacrificial feature; and removing the sacrificial feature to form an air gap.