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25 条记录 (耗时 0.031 秒)

    Method of arbitration for bus use request and system therefor
    12.
    发明授权
    Method of arbitration for bus use request and system therefor 失效
    总线使用请求仲裁方法及其系统

    公开(公告)号：US07380034B2

    公开(公告)日：2008-05-27

    申请号：US11110667

    申请日：2005-04-21

    申请人： Takafumi Fujiwara ,  Katsunori Kato ,  Noboru Yokoyama ,  Atsushi Date ,  Tadaaki Maeda

    发明人： Takafumi Fujiwara ,  Katsunori Kato ,  Noboru Yokoyama ,  Atsushi Date ,  Tadaaki Maeda

    IPC分类号： G06F13/00

    CPC分类号： G06F13/3625 ,  G06F13/364

    摘要： In plural master apparatus connected to a bus, a master apparatus issues, to an arbiter, a request signal requesting the use of the bus after a lapse of a predetermined interval when the use of the bus becomes necessary, while another master apparatus issues, to the arbiter, a request signal requesting the use of the bus immediately when the use of the bus becomes necessary. The arbiter grants a right to use the bus by equally handling the request signals from the master apparatus. Also there is prepared a signal indicating a traffic in the bus, and the request signal is issued after the lapse of the interval in case of a high traffic but it is issued immediately in case of a low traffic. It is thus possible to adjust the practical priority of the but use right in detail or to dynamically change such priority by the presence or absence of such interval or a length thereof.

    摘要翻译： 在连接到总线的多个主设备中，当需要使用总线时，主设备向仲裁器发出请求使用总线经过预定间隔的请求信号，而另一个主设备发出请求信号 仲裁器，当需要使用总线时，立即请求使用总线的请求信号。 仲裁器授权通过同样处理来自主设备的请求信号来使用总线的权利。 还准备了表示总线中的业务的信号，并且在高业务量的情况下经过间隔后发出请求信号，但是在流量低的情况下立即发出请求信号。 因此，可以详细地调整使用权的实际优先级，或者通过存在或不存在这样的间隔或其长度来动态地改变这种优先级。

    Memory controller
    13.
    发明申请
    Memory controller 失效
    内存控制器

    公开(公告)号：US20060236043A1

    公开(公告)日：2006-10-19

    申请号：US11378002

    申请日：2006-03-17

    申请人： Keigo Ogura ,  Takafumi Fujiwara

    发明人： Keigo Ogura ,  Takafumi Fujiwara

    IPC分类号： G06F13/00

    CPC分类号： G06F13/1689

    摘要： A memory system includes a memory and a plurality of memory controllers for accessing the memory. One of the plurality of memory controllers synchronizes the one of the plurality of memory controllers with the plurality of memory controllers.

    摘要翻译： 存储器系统包括用于访问存储器的存储器和多个存储器控制器。 多个存储器控制器中的一个将多个存储器控制器中的一个与多个存储器控制器同步。

    Bus management based on bus status
    15.
    发明授权
    Bus management based on bus status 失效

    公开(公告)号：US07062664B2

    公开(公告)日：2006-06-13

    申请号：US09917833

    申请日：2001-07-31

    申请人： Atsushi Date ,  Katsunori Kato ,  Noboru Yokoyama ,  Tadaaki Maeda ,  Takafumi Fujiwara

    发明人： Atsushi Date ,  Katsunori Kato ,  Noboru Yokoyama ,  Tadaaki Maeda ,  Takafumi Fujiwara

    IPC分类号： G06F1/26 ,  G05D3/12

    CPC分类号： G06F13/364

    摘要： A P bus from a CPU, an MC bus from a system memory, an IO bus to which an input/output device has been connected, and a G bus for transferring image data of a scanner/printer controller are connected to a system bus bridge (SBB). The SBB connects any of the P bus, G bus and IO bus as a master and any of the MC bus and IO bus as a slave in dependence upon a request from a master. At this time the P bus and IO bus can be connected in parallel with the G bus and MC bus. As a result, access to the memory by the scanner/printer controller can be carried out in parallel with use of the input/output device by the CPU. This makes it possible to process a large quantity of data, such as image data, efficiently.

    Image processing apparatus and method, and storage medium
    16.
    发明授权
    Image processing apparatus and method, and storage medium 有权

    公开(公告)号：US06992788B2

    公开(公告)日：2006-01-31

    申请号：US09927539

    申请日：2001-08-13

    申请人： Takafumi Fujiwara

    发明人： Takafumi Fujiwara

    IPC分类号： G06F15/00 ,  G06K1/00

    CPC分类号： G06T9/005

    摘要： The present invention efficiently compresses image data, and stores and manages the compressed data. Image data is compressed in tile unit having predetermined pixels and data packing is performed. The compressed data is compared with compressed data of a preceding packet. If these compressed data are different, the packet data is stored in a memory, and an entry address of the compressed data is stored in a packet table. Meanwhile, if the compressed data is equal to the compressed data of the preceding packet, the compressed data is not stored, but an entry address of the compressed data of the preceding packet is stored in a record of interest in the packet table, and a flag indicative of repetition of the preceding address is set in the packet of interest.

    Method of delaying bus request signals to arbitrate for bus use and system therefor
    17.
    发明授权
    Method of delaying bus request signals to arbitrate for bus use and system therefor 失效
    延迟总线请求信号以仲裁总线使用的方法及其系统

    公开(公告)号：US06952747B2

    公开(公告)日：2005-10-04

    申请号：US10314285

    申请日：2002-12-09

    申请人： Takafumi Fujiwara ,  Katsunori Kato ,  Noboru Yokoyama ,  Atsushi Date ,  Tadaaki Maeda

    发明人： Takafumi Fujiwara ,  Katsunori Kato ,  Noboru Yokoyama ,  Atsushi Date ,  Tadaaki Maeda

    IPC分类号： G06F13/362 ,  G06F13/00 ,  G06F13/16 ,  G06F13/36 ,  G06F13/364 ,  G06F13/372

    CPC分类号： G06F13/3625 ,  G06F13/364

    摘要： In plural master apparatus connected to a bus, a master apparatus issues, to an arbiter, a request signal requesting the use of the bus after a lapse of a predetermined interval when the use of the bus becomes necessary, while another master apparatus issues, to the arbiter, a request signal requesting the use of the bus immediately when the use of the bus becomes necessary. The arbiter grants a right to use the bus by equally handling the request signals from the master apparatus. Also there is prepared a signal indicating a traffic in the bus, and the request signal is issued after the lapse of the interval in case of a high traffic but it is issued immediately in case of a low traffic. It is thus possible to adjust the practical priority of the but use right in detail or to dynamically change such priority by the presence or absence of such interval or a length thereof.

    摘要翻译： 在连接到总线的多个主设备中，当需要使用总线时，主设备向仲裁器发出请求使用总线经过预定间隔的请求信号，而另一个主设备发出请求信号 仲裁器，当需要使用总线时，立即请求使用总线的请求信号。 仲裁器授权通过同样处理来自主设备的请求信号来使用总线的权利。 还准备了表示总线中的业务的信号，并且在高业务量的情况下经过间隔后发出请求信号，但是在流量低的情况下立即发出请求信号。 因此，可以详细地调整使用权的实际优先级，或者通过存在或不存在这样的间隔或其长度来动态地改变这种优先级。

    Method of arbitration for bus use request and system therefor
    18.
    发明申请
    Method of arbitration for bus use request and system therefor 失效
    总线使用请求仲裁方法及其系统

    公开(公告)号：US20050188139A1

    公开(公告)日：2005-08-25

    申请号：US11110667

    申请日：2005-04-21

    申请人： Takafumi Fujiwara ,  Katsunori Kato ,  Noburo Yokoyama ,  Atsushi Date ,  Tadaaki Maeda

    发明人： Takafumi Fujiwara ,  Katsunori Kato ,  Noburo Yokoyama ,  Atsushi Date ,  Tadaaki Maeda

    IPC分类号： G06F13/362 ,  G06F13/00 ,  G06F13/16 ,  G06F13/36 ,  G06F13/364 ,  G06F13/372

    CPC分类号： G06F13/3625 ,  G06F13/364

    摘要： In plural master apparatus connected to a bus, a master apparatus issues, to an arbiter, a request signal requesting the use of the bus after a lapse of a predetermined interval when the use of the bus becomes necessary, while another master apparatus issues, to the arbiter, a request signal requesting the use of the bus immediately when the use of the bus becomes necessary. The arbiter grants a right to use the bus by equally handling the request signals from the master apparatus. Also there is prepared a signal indicating a traffic in the bus, and the request signal is issued after the lapse of the interval in case of a high traffic but it is issued immediately in case of a low traffic. It is thus possible to adjust the practical priority of the but use right in detail or to dynamically change such priority by the presence or absence of such interval or a length thereof.

    摘要翻译： 在连接到总线的多个主设备中，当需要使用总线时，主设备向仲裁器发出请求使用总线经过预定间隔的请求信号，而另一个主设备发出请求信号 仲裁器，当需要使用总线时，立即请求使用总线的请求信号。 仲裁器授权通过同样处理来自主设备的请求信号来使用总线的权利。 还准备了表示总线中的业务的信号，并且在高业务量的情况下经过间隔后发出请求信号，但是在流量低的情况下立即发出请求信号。 因此，可以详细地调整使用权的实际优先级，或者通过存在或不存在这样的间隔或其长度来动态地改变这种优先级。

    IMAGE PROCESSING APPARATUS, CONTROL METHOD FOR THE IMAGE PROCESSING APPARATUS, AND STORAGE MEDIUM STORING COMPUTER PROGRAM FOR EXECUTING THE CONTROL METHOD OF THE IMAGE PROCESSING APPARATUS
    19.
    发明申请
    IMAGE PROCESSING APPARATUS, CONTROL METHOD FOR THE IMAGE PROCESSING APPARATUS, AND STORAGE MEDIUM STORING COMPUTER PROGRAM FOR EXECUTING THE CONTROL METHOD OF THE IMAGE PROCESSING APPARATUS 有权
    图像处理装置，图像处理装置的控制方法和用于执行图像处理装置的控制方法的存储中央存储计算机程序

    公开(公告)号：US20090268971A1

    公开(公告)日：2009-10-29

    申请号：US12419190

    申请日：2009-04-06

    申请人： Takafumi Fujiwara

    发明人： Takafumi Fujiwara

    IPC分类号： G06K9/36

    CPC分类号： H04N1/00838 ,  H04N1/00883 ,  H04N1/32128

    摘要： An image processing apparatus includes a production unit that can produce data by putting original image data into a first region and copy-forgery-inhibited-pattern image data into a second region, and a processing unit that can perform predetermined processing to the original image data put in the first region. The image processing apparatus further includes a composite image data producing unit that can produce composite image data based on both of the original image data to which the predetermined processing is performed and the copy-forgery-inhibited-pattern image data put in the second region of the data.

    摘要翻译： 一种图像处理装置包括：生产单元，其可以通过将原始图像数据放入第一区域和禁止复制伪造图案图像数据到第二区域中来产生数据;以及处理单元，其可以对原始图像数据执行预定处理 放在第一个地区。 该图像处理装置还包括合成图像数据产生单元，其可以基于执行预定处理的原始图像数据和放置在第二区域中的禁止复制伪造图案数据的两者来产生合成图像数据 数据。

    Control method for bus provided with internal switch
    20.
    发明授权
    Control method for bus provided with internal switch 有权
    配有内部开关的总线控制方式

    公开(公告)号：US07386634B2

    公开(公告)日：2008-06-10

    申请号：US10670300

    申请日：2003-09-26

    申请人： Kohei Murayama ,  Takafumi Fujiwara

    发明人： Kohei Murayama ,  Takafumi Fujiwara

    IPC分类号： G06F3/00 ,  G06F13/00 ,  G06F1/00

    CPC分类号： G06F13/4022 ,  G06F13/4217

    摘要： In a bus, which is provided with a switch having a plurality of master ports and a plurality of slave ports and can connect each of the plurality of master ports to an arbitrary port of the plurality of slave ports, an address phase that issues an address and a command and a data phase that issues write data are separated, and an address phase of next transaction can be issued before the data phase is completed. This improves performance of a system, in which a plurality of master modules and slave modules are connected through the bus.

    摘要翻译： 在总线中设置有具有多个主端口和多个从端口的交换机，并且可以将多个主端口中的每一个连接到多个从端口的任意端口，发出地址的地址阶段 并且发出写入数据的命令和数据阶段被分离，并且可以在数据阶段完成之前发出下一个事务的地址阶段。 这提高了通过总线连接多个主模块和从模块的系统的性能。