公开(公告)号：US20090230405A1

公开(公告)日：2009-09-17

申请号：US12382369

申请日：2009-03-13

申请人： Takeo Yamamoto ,  Takeshi Endo ,  Masaki Konishi ,  Hirokazu Fujiwara ,  Yukihiko Watanabe ,  Takashi Katsuno ,  Masayasu Ishiko

发明人： Takeo Yamamoto ,  Takeshi Endo ,  Masaki Konishi ,  Hirokazu Fujiwara ,  Yukihiko Watanabe ,  Takashi Katsuno ,  Masayasu Ishiko

IPC分类号： H01L29/24 ,  H01L21/04

CPC分类号： H01L29/872 ,  H01L29/0619 ,  H01L29/66136 ,  H01L29/66143 ,  H01L29/861

摘要： A manufacturing method of a diode includes: forming a P type semiconductor film on a N type semiconductor layer with a crystal growth method; forming a first metallic film on the P type semiconductor film so that the first metallic film contacts the P type semiconductor film with an ohmic contact; forming a mask having an opening on the first metallic film; etching a part of the first metallic film and a part of the P type semiconductor film via the opening so that a part of the N type semiconductor layer is exposed; and forming a second metallic film on the part of the N type semiconductor layer so that the second metallic film contacts the N type semiconductor layer with a Schottky contact.

摘要翻译： 二极管的制造方法包括：在晶体生长方法的N型半导体层上形成P型半导体膜; 在P型半导体膜上形成第一金属膜，使得第一金属膜与欧姆接触的P型半导体膜接触; 在所述第一金属膜上形成具有开口的掩模; 经由所述开口蚀刻所述第一金属膜的一部分和所述P型半导体膜的一部分，使得所述N型半导体层的一部分露出; 并且在N型半导体层的一部分上形成第二金属膜，使得第二金属膜以肖特基接触接触N型半导体层。

公开(公告)号：US08164100B2

公开(公告)日：2012-04-24

申请号：US12338151

申请日：2008-12-18

申请人： Hirokazu Fujiwara ,  Masaki Konishi ,  Eiichi Okuno

发明人： Hirokazu Fujiwara ,  Masaki Konishi ,  Eiichi Okuno

IPC分类号： H01L29/72

CPC分类号： H01L29/7813 ,  H01L29/04 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/872

摘要： A semiconductor device is provided in which the contact resistance of the interface between an electrode and the semiconductor substrate is reduced. The semiconductor device includes a 4H polytype SiC substrate, and an electrode formed on a surface of the substrate. A 3C polytype layer, which extends obliquely relative to the surface of the substrate and whose end portion at the substrate surface is in contact with the electrode, is formed at the surface of the substrate. The 3C polytype layer has a lower bandgap than 4H polytype. Hence, electrons present in the 4H polytype region pass through the 3C polytype layer and reach the electrode. More precisely, the width of the passageway of the electrons is determined by the thickness of the 3C polytype layer. Consequently, with this semiconductor device, in which the passageway of the electrons is narrow, the electrons are able to reach the electrode at a speed close to the theoretical value, by the quantum wire effect. In this way, the contact resistance can be reduced in the semiconductor device.

摘要翻译： 提供一种半导体器件，其中电极和半导体衬底之间的界面的接触电阻降低。 半导体器件包括4H多型SiC衬底和形成在衬底的表面上的电极。 形成在基板表面上相对于基板的表面倾斜地延伸并且其基板表面的端部与电极接触的3C多型层。 3C多型层具有比4H多型更低的带隙。 因此，存在于4H多型区域中的电子通过3C多型层并到达电极。 更准确地说，电子通道的宽度由3C多型层的厚度决定。 因此，通过电子通道窄的这种半导体器件，电子能够以接近理论值的速度通过量子线效应到达电极。 以这种方式，可以在半导体器件中降低接触电阻。

公开(公告)号：US20090160008A1

公开(公告)日：2009-06-25

申请号：US12343714

申请日：2008-12-24

申请人： Hirokazu Fujiwara ,  Masaki Konishi ,  Eiichi Okuno

发明人： Hirokazu Fujiwara ,  Masaki Konishi ,  Eiichi Okuno

IPC分类号： H01L29/47 ,  H01L21/441

CPC分类号： H01L29/872 ,  H01L29/861

摘要： A semiconductor device that includes an n-type semiconductor substrate and an upper electrode formed on an upper face of the semiconductor substrate and a method of manufacturing the semiconductor device are provided. A p-type semiconductor region is repeatedly formed in the semiconductor substrate in at least one direction parallel to the substrate plane so as to be exposed on an upper face of the semiconductor substrate. The upper electrode includes a metal electrode portion; and a semiconductor electrode portion made of a semiconductor material whose band gap is narrower than that of the semiconductor substrate. The semiconductor electrode portion is provided on each p-type semiconductor region exposed on the upper face of the semiconductor substrate. The metal electrode portion is in Schottky contact with an n-type semiconductor region exposed on the upper face of the semiconductor substrate, and is in ohmic contact with the semiconductor electrode portion.

摘要翻译： 提供一种半导体器件，其包括形成在半导体衬底的上表面上的n型半导体衬底和上电极以及制造半导体器件的方法。 在半导体衬底中以平行于衬底平面的至少一个方向重复地形成p型半导体区域，以便露出在半导体衬底的上表面上。 上部电极包括金属电极部分; 以及由半导体材料制成的半导体电极部分，该半导体材料的带隙比半导体衬底窄。 半导体电极部分设置在暴露在半导体衬底的上表面上的每个p型半导体区域上。 金属电极部分与暴露在半导体衬底的上表面上的n型半导体区域肖特基接触，并与半导体电极部分欧姆接触。

公开(公告)号：US08470672B2

公开(公告)日：2013-06-25

申请号：US13220756

申请日：2011-08-30

申请人： Takeshi Endo ,  Shinichiro Miyahara ,  Tomoo Morino ,  Masaki Konishi ,  Hirokazu Fujiwara ,  Jun Morimoto ,  Tsuyoshi Ishikawa ,  Takashi Katsuno ,  Yukihiko Watanabe

发明人： Takeshi Endo ,  Shinichiro Miyahara ,  Tomoo Morino ,  Masaki Konishi ,  Hirokazu Fujiwara ,  Jun Morimoto ,  Tsuyoshi Ishikawa ,  Takashi Katsuno ,  Yukihiko Watanabe

IPC分类号： H01L21/336 ,  H01L21/265

CPC分类号： H01L29/7813 ,  H01L21/30604 ,  H01L21/3065 ,  H01L29/1608 ,  H01L29/4236 ,  H01L29/66068

摘要： A method of manufacturing a semiconductor device includes forming a drift layer on a substrate; forming a base layer on the drift layer; forming a trench to penetrate the base layer and to reach the drift layer; rounding off a part of a shoulder corner and a part of a bottom corner of the trench; covering an inner wall of the trench with an organic film; implanting an impurity to a surface portion of the base layer; forming a source region by activating the implanted impurity; and removing the organic film after the source region is formed, in which the substrate, the drift layer, the base layer and the source region are made of silicon carbide, and the implanting and the activating of the impurity are performed under a condition that the trench is covered with the organic film.

摘要翻译： 制造半导体器件的方法包括在衬底上形成漂移层; 在漂移层上形成基层; 形成沟槽以穿透基层并到达漂移层; 将沟槽的一部分肩部角落和底角的一部分倒圆; 用有机膜覆盖沟槽的内壁; 将杂质注入基层的表面部分; 通过激活注入的杂质形成源区; 在形成源极区域之后除去有机膜，其中基板，漂移层，基极层和源极区域由碳化硅构成，并且杂质的注入和活化在 沟槽被有机膜覆盖。

公开(公告)号：US08436365B2

公开(公告)日：2013-05-07

申请号：US13031280

申请日：2011-02-21

申请人： Takeo Yamamoto ,  Takeshi Endo ,  Jun Morimoto ,  Hirokazu Fujiwara ,  Yukihiko Watanabe ,  Takashi Katsuno ,  Tsuyoshi Ishikawa

发明人： Takeo Yamamoto ,  Takeshi Endo ,  Jun Morimoto ,  Hirokazu Fujiwara ,  Yukihiko Watanabe ,  Takashi Katsuno ,  Tsuyoshi Ishikawa

IPC分类号： H01L29/16 ,  H01L29/47 ,  H01L29/872

CPC分类号： H01L29/47 ,  H01L21/0495 ,  H01L29/0619 ,  H01L29/063 ,  H01L29/1608 ,  H01L29/402 ,  H01L29/6606 ,  H01L29/872

摘要： A SiC semiconductor device having a Schottky barrier diode includes: a substrate made of SiC and having a first conductive type, wherein the substrate includes a main surface and a rear surface; a drift layer made of SiC and having the first conductive type, wherein the drift layer is disposed on the main surface of the substrate and has an impurity concentration lower than the substrate; a Schottky electrode disposed on the drift layer and has a Schottky contact with a surface of the drift layer; and an ohmic electrode disposed on the rear surface of the substrate. The Schottky electrode directly contacts the drift layer in such a manner that a lattice of the Schottky electrode is matched with a lattice of the drift layer.

摘要翻译： 具有肖特基势垒二极管的SiC半导体器件包括：由SiC制成并具有第一导电类型的衬底，其中所述衬底包括主表面和后表面; 由SiC制成并具有第一导电类型的漂移层，其中所述漂移层设置在所述衬底的主表面上并且具有低于所述衬底的杂质浓度; 肖特基电极，设置在漂移层上并与漂移层的表面具有肖特基接触; 以及设置在基板的后表面上的欧姆电极。 肖特基电极以使得肖特基电极的晶格与漂移层的晶格匹配的方式直接接触漂移层。

公开(公告)号：US20110204383A1

公开(公告)日：2011-08-25

申请号：US13031280

申请日：2011-02-21

申请人： Takeo YAMAMOTO ,  Takeshi Endo ,  Jun Morimoto ,  Hirokazu Fujiwara ,  Yukihiko Watanabe ,  Takashi Katsuno ,  Tsuyoshi Ishikawa

发明人： Takeo YAMAMOTO ,  Takeshi Endo ,  Jun Morimoto ,  Hirokazu Fujiwara ,  Yukihiko Watanabe ,  Takashi Katsuno ,  Tsuyoshi Ishikawa

IPC分类号： H01L29/24 ,  H01L21/329 ,  B82Y99/00 ,  B82Y40/00

CPC分类号： H01L29/47 ,  H01L21/0495 ,  H01L29/0619 ,  H01L29/063 ,  H01L29/1608 ,  H01L29/402 ,  H01L29/6606 ,  H01L29/872

摘要： A SiC semiconductor device having a Schottky barrier diode includes: a substrate made of SiC and having a first conductive type, wherein the substrate includes a main surface and a rear surface; a drift layer made of SiC and having the first conductive type, wherein the drift layer is disposed on the main surface of the substrate and has an impurity concentration lower than the substrate; a Schottky electrode disposed on the drift layer and has a Schottky contact with a surface of the drift layer; and an ohmic electrode disposed on the rear surface of the substrate. The Schottky electrode directly contacts the drift layer in such a manner that a lattice of the Schottky electrode is matched with a lattice of the drift layer.

摘要翻译： 具有肖特基势垒二极管的SiC半导体器件包括：由SiC制成并具有第一导电类型的衬底，其中所述衬底包括主表面和后表面; 由SiC制成并具有第一导电类型的漂移层，其中所述漂移层设置在所述衬底的主表面上并且具有低于所述衬底的杂质浓度; 肖特基电极，设置在漂移层上并与漂移层的表面具有肖特基接触; 以及设置在基板的后表面上的欧姆电极。 肖特基电极以使得肖特基电极的晶格与漂移层的晶格匹配的方式直接接触漂移层。

公开(公告)号：US10020390B2

公开(公告)日：2018-07-10

申请号：US15107313

申请日：2014-08-04

申请人： Jun Saito ,  Hirokazu Fujiwara ,  Tomoharu Ikeda ,  Yukihiko Watanabe ,  Toshimasa Yamamoto

发明人： Jun Saito ,  Hirokazu Fujiwara ,  Tomoharu Ikeda ,  Yukihiko Watanabe ,  Toshimasa Yamamoto

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/40 ,  H01L29/16 ,  H01L29/66 ,  H01L21/04 ,  H01L21/265

CPC分类号： H01L29/7811 ,  H01L21/047 ,  H01L21/26586 ,  H01L29/0623 ,  H01L29/063 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/408 ,  H01L29/66068 ,  H01L29/7813

摘要： A technique achieving a higher voltage resistance by a depletion layer extending quickly within a circumferential region is provided. A semiconductor device includes an element region in which an insulated gate type switching element is provided and a circumferential region adjacent to the element region. First and second trenches are provided in the circumferential region. A front surface region of the second-conductivity-type is provided between the first and second trenches. First and second bottom surface regions of the second-conductivity-type are provided in bottom surface ranges of the first and second trenches. First and second side surface regions of the second-conductivity-type connecting the front surface region and the first or second bottom surface region is provided along side surfaces of the first and second trenches. Low area density regions are provided in at least parts of the first and second side surface regions.

公开(公告)号：US09780205B2

公开(公告)日：2017-10-03

申请号：US15104332

申请日：2014-08-04

申请人： Jun Saito ,  Hirokazu Fujiwara ,  Tomoharu Ikeda ,  Yukihiko Watanabe ,  Toshimasa Yamamoto

发明人： Jun Saito ,  Hirokazu Fujiwara ,  Tomoharu Ikeda ,  Yukihiko Watanabe ,  Toshimasa Yamamoto

IPC分类号： H01L29/78 ,  H01L21/761 ,  H01L29/06 ,  H01L29/16 ,  H01L29/66 ,  H01L21/04

CPC分类号： H01L29/7811 ,  H01L21/046 ,  H01L21/761 ,  H01L29/0623 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7813

摘要： A technique disclosed herein improves a voltage resistance of an insulated gate type semiconductor device. A provided method is a method for manufacturing an insulated gate type switching device configured to switch between a front surface electrode and a rear surface electrode. The method includes implanting a first kind of second conductivity type impurities to bottom surfaces of gate trenches and diffusing the implanted first kind of second conductivity type impurities, and implanting a second kind of second conductivity type impurities to the bottom surfaces of the circumferential trenches and diffusing the implanted second kind of second conductivity type impurities.

公开(公告)号：US09142411B2

公开(公告)日：2015-09-22

申请号：US14090424

申请日：2013-11-26

申请人： Masatoshi Tsujimura ,  Hirokazu Fujiwara ,  Tomoo Morino ,  Narumasa Soejima

发明人： Masatoshi Tsujimura ,  Hirokazu Fujiwara ,  Tomoo Morino ,  Narumasa Soejima

IPC分类号： H01L21/00 ,  H01L21/04 ,  H01L21/673 ,  H01L29/16

CPC分类号： H01L21/046 ,  H01L21/67303 ,  H01L29/1608

摘要： A method for producing a semiconductor device includes: an arranging process of arranging a plurality of silicon carbide wafers having opposed first and surfaces so that the first surface and the second surface of adjacent silicon carbide wafers face each other and are separated in parallel; and a heat treatment process of heating the arranged plurality of silicon carbide wafers so that the first surface of each silicon carbide wafer becomes higher in temperature than the second surface thereof, and, in the adjacent silicon carbide wafers, the second surface of one silicon carbide wafer becomes higher in temperature than the first surface of the other silicon carbide wafer that faces the second surface.

摘要翻译： 一种半导体器件的制造方法，其特征在于，包括：配置多个具有相对的第一面和表面的碳化硅晶片的布置处理，使得相邻碳化硅晶片的第一表面和第二表面彼此面对并且彼此平行分离; 以及加热配置的多个碳化硅晶片的热处理工序，使得碳化硅晶片的第一表面的温度比其第二表面变高，并且在相邻的碳化硅晶片中，一个碳化硅的第二表面 晶片的温度比面向第二表面的另一个碳化硅晶片的第一表面变得更高。

公开(公告)号：US08748975B2

公开(公告)日：2014-06-10

申请号：US13712343

申请日：2012-12-12

申请人： Hirokazu Fujiwara ,  Yukihiko Watanabe ,  Narumasa Soejima ,  Toshimasa Yamamoto ,  Yuichi Takeuchi

发明人： Hirokazu Fujiwara ,  Yukihiko Watanabe ,  Narumasa Soejima ,  Toshimasa Yamamoto ,  Yuichi Takeuchi

IPC分类号： H01L29/66 ,  H01L21/336

CPC分类号： H01L29/66666 ,  H01L21/26506 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/167 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/66068 ,  H01L29/7397 ,  H01L29/7813 ,  H01L29/7827

摘要： A switching element is provided having a semiconductor substrate. A trench gate electrode is formed in the upper surface of the semiconductor substrate. An n-type first semiconductor region, a p-type second semiconductor region, and an n-type third semiconductor region are formed in a region in contact with a gate insulating film in the semiconductor substrate. At a position below the second semiconductor region, there is formed a p-type fourth semiconductor region connected to the second semiconductor region and opposing the gate insulating film via the third semiconductor region and containing boron. A high-concentration-carbon containing region having a carbon concentration higher than that of a semiconductor region exposed on the lower surface of the semiconductor substrate is formed in at least a part of the portion of the third semiconductor region, positioned between the fourth semiconductor region and the gate insulating film, that is in contact with the fourth semiconductor region.

摘要翻译： 提供了具有半导体衬底的开关元件。 沟槽栅电极形成在半导体衬底的上表面中。 在与半导体衬底中的栅极绝缘膜接触的区域中形成n型第一半导体区域，p型第二半导体区域和n型第三半导体区域。 在第二半导体区域下方的位置处，形成连接到第二半导体区域的p型第四半导体区域，并且经由第三半导体区域与栅极绝缘膜相对并且含有硼。 在第三半导体区域的至少一部分中，形成具有比在半导体衬底的下表面露出的半导体区域更高的碳浓度的高浓度含碳区域，位于第四半导体区域 以及与第四半导体区域接触的栅极绝缘膜。