-
11.发明授权公开(公告)号：US07376187B2
公开(公告)日：2008-05-20
申请号：US11686807
申请日：2007-03-15
IPC分类号： H04N7/18
CPC分类号： H04N19/69 , H04N19/152 , H04N19/159 , H04N19/176 , H04N19/187 , H04N19/37 , H04N19/46 , H04N19/52 , H04N19/61 , H04N19/65 , H04N19/66 , H04N19/70 , H04N19/89 , H04N19/93
摘要： A coding and/or decoding system includes: a code-word table for storing therein a plurality of code words, which are capable of being decoded both in forward and backward directions and which are formed so that delimiters of the code words are capable of being identified by a predetermined weight of the code words, so that the code words correspond to different source symbols; an encoder for selecting code words corresponding to inputted source symbols from the code-word table; and a synchronization interval setting part for preparing coded data every predetermined interval using the code words selected by the encoder and for inserting stuffing codes capable of being decoded in the backward direction. Thus, it is possible to decrease useless bit patterns to enhance the coding efficiency by smaller amounts of calculation and storage, and to decode variable length codes both in the forward and backward directions even if the synchronization interval is set every interval using the stuffing bits.
-
公开(公告)号：US20070283228A1
公开(公告)日：2007-12-06
申请号：US11770317
申请日：2007-06-28
IPC分类号： H03M13/00
CPC分类号： H04L1/0042 , G11B20/1813 , G11B27/3027 , H03M13/15 , H03M13/152 , H03M13/23 , H03M13/33 , H03M13/356 , H04J3/0602 , H04L1/0041 , H04L1/0047 , H04L1/0068 , H04L1/007 , H04L1/0075 , H04L1/0079 , H04L1/0083 , H04L7/041 , H04L7/048 , H04L2001/0098 , H04N7/56 , H04N19/00 , H04N19/61 , H04N19/68 , H04N19/70 , H04N19/89
摘要： In a coding system wherein an error correction/detect-ion coding is combined with a synchronization recovering technique using a synchronization code, the problems of a pseudo synchronization and a step out due to error detect-ion are solved. There is provided a coding part 212 for coding an input multiplexed code string 201 to an error correcting/detecting code comprising an information bit and a check bit, and code string assembling part 213 for inserting a synchronization code into any one of a plurality of periodically predetermined synchronization code inserting positions in the code string 201, for arranging the information bit at an optional position in the code string, and for arranging the check bit at a position other than the synchronization code inserting positions in the code string 201 to assemble an output code string 205.
摘要翻译： 在将纠错/检测离子编码与使用同步码的同步恢复技术组合的编码系统中，解决了由于错误检测引起的伪同步和失步的问题。 提供了一个用于将输入的多路复用代码串201编码到包括信息位和校验位的纠错/检测码的编码部分212，以及代码串组合部分213，用于将同步码插入多个周期性的任一个 代码串201中的预定同步代码插入位置，用于将信息位布置在代码串中的可选位置处，并且用于将校验位排列在代码串201中的同步代码插入位置以外的位置，以组合输出 代码串205。
-
公开(公告)号：US20070283226A1
公开(公告)日：2007-12-06
申请号：US11770231
申请日：2007-06-28
IPC分类号： H03M13/00
CPC分类号： H04L1/0042 , G11B20/1813 , G11B27/3027 , H03M13/15 , H03M13/152 , H03M13/23 , H03M13/33 , H03M13/356 , H04J3/0602 , H04L1/0041 , H04L1/0047 , H04L1/0068 , H04L1/007 , H04L1/0075 , H04L1/0079 , H04L1/0083 , H04L7/041 , H04L7/048 , H04L2001/0098 , H04N7/56 , H04N19/00 , H04N19/61 , H04N19/68 , H04N19/70 , H04N19/89
摘要： In a coding system wherein an error correction/detect-ion coding is combined with a synchronization recovering technique using a synchronization code, the problems of a pseudo synchronization and a step out due to error detect-ion are solved. There is provided a coding part 212 for coding an input multiplexed code string 201 to an error correcting-/detecting code comprising an information bit and a check bit, and code string assembling part 213 for inserting a synchronization code into any one of a plurality of periodically predetermined synchronization code inserting positions in the code string 201, for arranging the information bit at an optional position in the code string, and for arranging the check bit at a position other than the synchronization code inserting positions in the code string 201 to assemble an output code string 205.
摘要翻译： 在将纠错/检测离子编码与使用同步码的同步恢复技术组合的编码系统中，解决了由于错误检测引起的伪同步和失步的问题。 提供了编码部分212，用于将输入的多路复用代码串201编码到包括信息位和校验位的纠错/检测码，以及代码串组合部分213，用于将同步码插入到多个 在代码串201中周期性地预定的同步代码插入位置，用于将信息位布置在代码串中的可选位置处，并且用于将校验位排列在代码串201中的同步代码插入位置以外的位置，以组合 输出代码串205。
-
14.发明申请Moving picture coding and/or decoding systems, and variable-length coding and/or decoding system 审中-公开运动图像编码和/或解码系统以及可变长度编码和/或解码系统公开(公告)号：US20070160149A1
公开(公告)日：2007-07-12
申请号：US11716555
申请日：2007-03-12
IPC分类号： H04N11/04
CPC分类号： H04N19/69 , H04N19/152 , H04N19/159 , H04N19/176 , H04N19/187 , H04N19/37 , H04N19/46 , H04N19/52 , H04N19/61 , H04N19/65 , H04N19/66 , H04N19/70 , H04N19/89 , H04N19/93
摘要： A coding and/or decoding system includes: a code-word table for storing therein a plurality of code words, which are capable of being decoded both in forward and backward directions and which are formed so that delimiters of the code words are capable of being identified by a predetermined weight of the code words, so that the code words correspond to different source symbols; an encoder for selecting code words corresponding to inputted source symbols from the code-word table; and a synchronization interval setting part for preparing coded data every predetermined interval using the code words selected by the encoder and for inserting stuffing codes capable of being decoded in the backward direction. Thus, it is possible to decrease useless bit patterns to enhance the coding efficiency by smaller amounts of calculation and storage, and to decode variable length codes both in the forward and backward directions even if the synchronization interval is set every interval using the stuffing bits.
摘要翻译： 编码和/或解码系统包括：码字表，用于在其中存储多个码字，其能够在前向和后向被解码，并且形成为使得码字的分隔符能够被 由代码字的预定权重识别，使得码字对应于不同的源符号; 编码器，用于从码字表中选择与输入的源符号对应的码字; 以及同步间隔设定部分，用于使用由编码器选择的代码字，每隔预定间隔准备编码数据，并用于插入能够沿向后方向解码的填充码。 因此，可以减少无用的位模式，通过更少的计算和存储量来提高编码效率，并且即使在使用填充位的每个间隔设置同步间隔的情况下，也可以在正向和反向方向上解码可变长度代码。
-
15.发明申请公开(公告)号：US20070160148A1
公开(公告)日：2007-07-12
申请号：US11716554
申请日：2007-03-12
IPC分类号： H04N11/04
CPC分类号： H04N19/69 , H04N19/152 , H04N19/159 , H04N19/176 , H04N19/187 , H04N19/37 , H04N19/46 , H04N19/52 , H04N19/61 , H04N19/65 , H04N19/66 , H04N19/70 , H04N19/89 , H04N19/93
摘要： A coding and/or decoding system includes: a code-word table for storing therein a plurality of code words, which are capable of being decoded both in forward and backward directions and which are formed so that delimiters of the code words are capable of being identified by a predetermined weight of the code words, so that the code words correspond to different source symbols; an encoder for selecting code words corresponding to inputted source symbols from the code-word table; and a synchronization interval setting part for preparing coded data every predetermined interval using the code words selected by the encoder and for inserting stuffing codes capable of being decoded in the backward direction. Thus, it is possible to decrease useless bit patterns to enhance the coding efficiency by smaller amounts of calculation and storage, and to decode variable length codes both in the forward and backward directions even if the synchronization interval is set every interval using the stuffing bits.
-
公开(公告)号：US20060218463A1
公开(公告)日：2006-09-28
申请号：US11418203
申请日：2006-05-05
IPC分类号： H03M13/00
CPC分类号： H03M13/27 , G11B20/1813 , G11B27/3027 , H03M13/33 , H03M13/356 , H04J3/0602 , H04J3/0605 , H04J3/07 , H04L1/004 , H04L1/0041 , H04L1/0046 , H04L1/0072 , H04L1/0083 , H04L7/041 , H04L7/048 , H04L2001/0098 , H04N7/56 , H04N19/00 , H04N19/61 , H04N19/70 , H04N19/89 , H04N21/2383 , H04N21/4382
摘要： An output coding apparatus includes a coder for coding an inputted bitstream to an error correction and/or detection code composed of information bits and check bits; and a bitstream assembling section for assembling an outputted bitstream by inserting a synchronization code at any one of a plurality of synchronization code insertion positions previously determined in the outputted bitstream, arranging the information bits at any desired positions of the bitstream, and by arranging the check bits at positions other than the synchronization code insertion positions in the bitstream. Therefore, when the coding apparatus is combined with a resynchronization method using both an error correction and/or detection code and a synchronization code, it is possible to solve a problem caused by pseudo-synchronization or synchronization-loss pull-out or step-out due to erroneous detection of the synchronization code.
-
公开(公告)号：US20060206788A1
公开(公告)日：2006-09-14
申请号：US11418106
申请日：2006-05-05
IPC分类号： H03M13/03
CPC分类号： H03M13/27 , G11B20/1813 , G11B27/3027 , H03M13/33 , H03M13/356 , H04J3/0602 , H04J3/0605 , H04J3/07 , H04L1/004 , H04L1/0041 , H04L1/0046 , H04L1/0072 , H04L1/0083 , H04L7/041 , H04L7/048 , H04L2001/0098 , H04N7/56 , H04N19/00 , H04N19/61 , H04N19/70 , H04N19/89 , H04N21/2383 , H04N21/4382
摘要： An output coding apparatus includes a coder for coding an inputted bitstream to an error correction and/or detection code composed of information bits and check bits; and a bitstream assembling section for assembling an outputted bitstream by inserting a synchronization code at any one of a plurality of synchronization code insertion positions previously determined in the outputted bitstream, arranging the information bits at any desired positions of the bitstream, and by arranging the check bits at positions other than the synchronization code insertion positions in the bitstream. Therefore, when the coding apparatus is combined with a resynchronization method using both an error correction and/or detection code and a synchronization code, it is possible to solve a problem caused by pseudo-synchronization or synchronization-loss pull-out or step-out due to erroneous detection of the synchronization code.
-
公开(公告)号：US20060206787A1
公开(公告)日：2006-09-14
申请号：US11418105
申请日：2006-05-05
IPC分类号： H03M13/03
CPC分类号： H03M13/27 , G11B20/1813 , G11B27/3027 , H03M13/33 , H03M13/356 , H04J3/0602 , H04J3/0605 , H04J3/07 , H04L1/004 , H04L1/0041 , H04L1/0046 , H04L1/0072 , H04L1/0083 , H04L7/041 , H04L7/048 , H04L2001/0098 , H04N7/56 , H04N19/00 , H04N19/61 , H04N19/70 , H04N19/89 , H04N21/2383 , H04N21/4382
摘要： An output coding apparatus includes a coder for coding an inputted bitstream to an error correction and/or detection code composed of information bits and check bits; and a bitstream assembling section for assembling an outputted bitstream by inserting a synchronization code at any one of a plurality of synchronization code insertion positions previously determined in the outputted bitstream, arranging the information bits at any desired positions of the bitstream, and by arranging the check bits at positions other than the synchronization code insertion positions in the bitstream. Therefore, when the coding apparatus is combined with a resynchronization method using both an error correction and/or detection code and a synchronization code, it is possible to solve a problem caused by pseudo-synchronization or synchronization-loss pull-out or step-out due to erroneous detection of the synchronization code.
-
公开(公告)号：US20060195764A1
公开(公告)日：2006-08-31
申请号：US11412121
申请日：2006-04-27
IPC分类号： H03M13/00
CPC分类号： H03M13/27 , G11B20/1813 , G11B27/3027 , H03M13/33 , H03M13/356 , H04J3/0602 , H04J3/0605 , H04J3/07 , H04L1/004 , H04L1/0041 , H04L1/0046 , H04L1/0072 , H04L1/0083 , H04L7/041 , H04L7/048 , H04L2001/0098 , H04N7/56 , H04N19/00 , H04N19/61 , H04N19/70 , H04N19/89 , H04N21/2383 , H04N21/4382
摘要： An output coding apparatus includes a coder for coding an inputted bitstream to an error correction and/or detection code composed of information bits and check bits; and a bitstream assembling section for assembling an outputted bitstream by inserting a synchronization code at any one of a plurality of synchronization code insertion positions previously determined in the outputted bitstream, arranging the information bits at any desired positions of the bitstream, and by arranging the check bits at positions other than the synchronization code insertion positions in the bitstream. Therefore, when the coding apparatus is combined with a resynchronization method using both an error correction and/or detection code and a synchronization code, it is possible to solve a problem caused by pseudo-synchronization or synchronization-loss pull-out or step-out due to erroneous detection of the synchronization code.
-
公开(公告)号：US07032137B2
公开(公告)日：2006-04-18
申请号：US09983506
申请日：2001-10-24
IPC分类号： H04L7/00
CPC分类号： H04N21/435 , G11B20/1813 , G11B27/3027 , H04J3/0602 , H04L1/0041 , H04L1/0045 , H04L1/0083 , H04L7/041 , H04L7/048 , H04L2001/0098 , H04N7/56 , H04N19/00 , H04N19/61 , H04N19/70 , H04N19/89 , H04N21/23424 , H04N21/235 , H04N21/2383 , H04N21/2404 , H04N21/242 , H04N21/4382
摘要： In a coding system wherein an error correction/detect-ion coding is combined with a synchronization recovering technique using a synchronization code, the problems of a pseudo synchronization and a step out due to error detect-ion are solved. There is provided a coding part for coding an input multiplexed code string to an error correcting/detecting code comprising an information bit and a check bit, and code string assembling part for inserting a synchronization code into any one of a plurality of periodically predetermined synchronization code inserting positions in a code string, for arranging the information bit at an optional position in the code string, and for arranging the check bit at a position other than the synchronization code inserting positions in the code string to assemble an output code string.
-
-
-
-
-
-
-
-
-
搜索结果
483 条记录 (耗时 0.041 秒)
