公开(公告)号：US5661320A

公开(公告)日：1997-08-26

申请号：US475763

申请日：1995-06-07

申请人： Hiroyuki Moriya

发明人： Hiroyuki Moriya

IPC分类号： H01L21/20 ,  H01L21/02 ,  H01L21/304 ,  H01L21/822 ,  H01L21/8242 ,  H01L21/84 ,  H01L27/04 ,  H01L27/10 ,  H01L27/108 ,  H01L27/12 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L27/10858 ,  H01L21/84 ,  H01L27/1082 ,  H01L27/1203

摘要： In method of manufacturing a DRAM by using a laminate SOI technique, which makes it possible to form a thin semiconductor film of a uniform thickness, the method includes steps of forming a step portion on a major surface of a silicon substrate, forming an insulating film on the major surface of the silicon substrate, forming a capacitor which is connected to the step potion through a contact hole formed through the insulating film on the step portion, grinding the silicon substrate from the other major surface thereof after a support substrate is laminated onto the silicon substrate to remain the step portion, forming a thin silicon film on the insulating film by lateral epitaxial growth process based on the silicon of the remaining step portion serving as a seed for the lateral epitaxial growth, and forming a MOS transistor in the thin silicon film.

摘要翻译： 通过使用层压SOI技术制造DRAM的方法，其可以形成均匀厚度的薄半导体膜，该方法包括以下步骤：在硅衬底的主表面上形成台阶部分，形成绝缘膜 在硅基板的主表面上形成电容器，该电容器通过台阶部分上的绝缘膜形成的接触孔连接到台阶部分，在将支撑基板层压到其上之后，从另一个主表面研磨硅基板 所述硅衬底保持所述台阶部分，通过横向外延生长工艺在所述绝缘膜上形成薄硅膜，所述外延生长工艺基于用作横向外延生长的剩余步骤部分的硅，并且形成薄的 硅膜。

公开(公告)号：US20050020013A1

公开(公告)日：2005-01-27

申请号：US10922141

申请日：2004-08-19

申请人： Hiroyuki Moriya ,  Toshio Kobayashi

发明人： Hiroyuki Moriya ,  Toshio Kobayashi

IPC分类号： H01L21/8247 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/115 ,  H01L29/51 ,  H01L29/788 ,  H01L29/792 ,  G11C11/34

CPC分类号： H01L29/513 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/518 ,  H01L29/7923 ,  Y10S257/908

摘要： The present invention prevents production of residue which causes short-circuit between word lines. A memory cell comprises a channel formation region CH, charge storage films CSF each comprised of a plurality of stacked dielectric films, two storages comprised of regions of the charge storage films CSF overlapping the two ends of the channel formation region CH, a single-layer dielectric film DF2 contacting the channel formation region CH between the storages, auxiliary layers (for example, bit lines BL1 and BL2) formed on two impurity regions S/D, two first control electrodes CG1 and CG2 formed on the auxiliary layers with dielectric film interposed and positioned on the storages, and a second control electrode WL buried in a state insulated from the first control electrodes CG1 and CG2 in a space between them and contacting the single-layer dielectric film DF2. Since the main regions on facing surfaces of the first control electrodes CG1 and CG2 become forward tapered, conductive residue is not left at the time of processing the second control electrode WL.

摘要翻译： 本发明防止产生在字线之间短路的残留物。 存储单元包括沟道形成区域CH，每个由多个堆叠的电介质膜组成的电荷存储膜CSF，由与沟道形成区域CH的两端重叠的电荷存储膜CSF的区域组成的两个存储器，单层 电介质膜DF2与存储器之间的沟道形成区域CH，形成在两个杂质区域S / D上的辅助层（例如位线BL1和BL2）接触，形成在辅助层上的两个第一控制电极CG1和CG2， 并且位于存储器上，以及第二控制电极WL，其在与它们之间的空间中与第一控制电极CG1和CG2绝缘的状态下被掩埋并与单层电介质膜DF2接触。 由于第一控制电极CG1和CG2的相对表面上的主要区域向前渐变，所以在处理第二控制电极WL时不会导致残留物。

公开(公告)号：US06803620B2

公开(公告)日：2004-10-12

申请号：US10168921

申请日：2002-10-02

申请人： Hiroyuki Moriya ,  Toshio Kobayashi

发明人： Hiroyuki Moriya ,  Toshio Kobayashi

IPC分类号： H01L27108

CPC分类号： H01L29/513 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/518 ,  H01L29/7923 ,  Y10S257/908

摘要： The present invention prevents production of residue which causes short-circuit between word lines. A memory cell comprises a channel formation region CH, charge storage films CSF each comprised of a plurality of stacked dielectric films, two storages comprised of regions of the charge storage films CSF-overlapping the two ends of the channel formation region CH, a single-layer dielectric film DF2 contacting the channel formation region CH between the storages, auxiliary layers (for example, bit lines BL1 and BL2) formed on two impurity regions S/D, two first control-electrodes CG1 and CG2 formed on the auxiliary layers with dielectric film interposed and positioned on the storages, and a second control electrode WL buried in a state insulated from the first control electrodes CG1 and CG2 in a space between them and contacting the single-layer dielectric film DF2. Since the main regions on facing surfaces of the first control electrodes CG1 and CG2 become forward tapered, conductive residue is not left at the time of processing the second control electrode WL.

摘要翻译： 本发明防止产生在字线之间短路的残留物。 存储单元包括沟道形成区域CH，每个由多个堆叠的电介质膜构成的电荷存储膜CSF，由电荷存储膜的区域组成的两个存储区域CSF，与沟道形成区域CH的两端重叠， 接触存储器之间的沟道形成区域CH的层间电介质膜DF2，形成在两个杂质区域S / D上的辅助层（例如，位线BL1和BL2），形成在具有电介质的辅助层上的两个第一控制电极CG1和CG2 插入并定位在存储器上的膜;以及第二控制电极WL，其在与它们之间的空间中与第一控制电极CG1和CG2绝缘的状态下被掩埋并与单层电介质膜DF2接触。 由于第一控制电极CG1和CG2的相对表面上的主要区域向前渐变，所以在处理第二控制电极WL时不会导致残留物。

公开(公告)号：US06721205B2

公开(公告)日：2004-04-13

申请号：US09735938

申请日：2000-12-14

申请人： Toshio Kobayashi ,  Hiroyuki Moriya ,  Ichiro Fujiwara

发明人： Toshio Kobayashi ,  Hiroyuki Moriya ,  Ichiro Fujiwara

IPC分类号： G11C1604

CPC分类号： H01L27/11521 ,  G11C16/0475 ,  G11C16/0491 ,  G11C16/10 ,  H01L27/115 ,  H01L29/66825 ,  H01L29/7923

摘要： A nonvolatile semiconductor memory device with high reliability (free from troubles in storing data), a high charge injection efficiency, and enabling parallel operation in a VG cell array, includes channel forming regions, a charge storing film which consists of stacked dielectric films and is capable of storing a charge, two storage portions forming parts of the charge storing film and overlapping the channel forming regions, a single layer dielectric film between the storage portions and in contact with the channel forming region, a control gate electrode on the single layer dielectric film, and a memory gate electrode on the storage portions.

摘要翻译： 具有高可靠性（不存储数据的麻烦），高电荷注入效率和在VG电池阵列中实现并行操作的非易失性半导体存储器件包括沟道形成区域，电荷存储膜，其由堆叠的电介质膜组成，并且是 能够存储电荷的两个存储部分，形成电荷存储膜的部分并且与沟道形成区重叠的两个存储部分，在存储部分之间并与沟道形成区域接触的单层电介质膜，单层电介质上的控制栅电极 膜和存储部分上的存储栅电极。

公开(公告)号：US5506163A

公开(公告)日：1996-04-09

申请号：US285722

申请日：1994-08-04

申请人： Hiroyuki Moriya

发明人： Hiroyuki Moriya

IPC分类号： H01L21/20 ,  H01L21/02 ,  H01L21/304 ,  H01L21/822 ,  H01L21/8242 ,  H01L21/84 ,  H01L27/04 ,  H01L27/10 ,  H01L27/108 ,  H01L27/12

CPC分类号： H01L27/10858 ,  H01L21/84 ,  H01L27/1082 ,  H01L27/1203

摘要： In a method of manufacturing a DRAM by using a laminate SOI technique, which makes it possible to form a thin semiconductor film of a uniform thickness, the method includes steps of forming a step portion on a major surface of a silicon substrate, forming an insulating film on the major surface of the silicon substrate, forming a capacitor which is connected to the step potion through a contact hole formed through the insulating film on the step portion, grinding the silicon substrate from the other major surface thereof after a support substrate is laminated onto the silicon substrate to remain the step portion, forming a thin silicon film on the insulating film by lateral epitaxial growth process based on the silicon of the remaining step portion serving as a seed for the lateral epitaxial growth, and forming a MOS transistor in the thin silicon film.

摘要翻译： 在通过使用层叠SOI技术制造DRAM的方法中，其可以形成均匀厚度的薄半导体膜，该方法包括以下步骤：在硅衬底的主表面上形成台阶部分，形成绝缘体 在硅基板的主表面上形成电容器，该电容器通过台阶上通过绝缘膜形成的接触孔连接到台阶部分，在支撑基板被层叠之后从另一个主表面研磨硅基板 到硅衬底上以保持台阶部分，通过横向外延生长工艺在绝缘膜上形成薄硅膜，该工艺基于用作横向外延生长的剩余步骤部分的硅，并形成MOS晶体管 薄硅膜。

公开(公告)号：US08394980B2

公开(公告)日：2013-03-12

申请号：US13584166

申请日：2012-08-13

申请人： Hiroyuki Moriya

发明人： Hiroyuki Moriya

IPC分类号： C07F7/18

CPC分类号： C07C227/18 ,  C07C229/26 ,  C07C231/02 ,  C08G77/26 ,  C08G77/388 ,  C07C237/06

摘要： An amino acid-modified organopolysiloxane is provided. It has an amino acid derivative bonded to at least one silicon atom of the organopolysiloxane segment constituting the backbone of the organopolysiloxane via an amide bond represented by the following general formula (1): wherein X and Y are independently a C1-10 divalent hydrocarbon group; m is an integer of 0 to 4; Ra is hydrogen atom, a monovalent hydrocarbon group containing 1 to 4 carbon atoms, or an organic group represented by the following general formula (2): (wherein Rb is hydrogen atom, a C1-7 monovalent hydrocarbon group, an alkaline metal, or an alkaline earth metal, and Rc is independently hydrogen atom, hydroxy group, or a C1-10 monovalent hydrocarbon group optionally containing oxygen atom, sulfur atom, or nitrogen atom); and Z is an organic group represented by the general formula (2).

摘要翻译： 提供氨基酸改性的有机聚硅氧烷。 其具有通过由以下通式（1）表示的酰胺键与构成有机聚硅氧烷的主链的有机聚硅氧烷链段的至少一个硅原子键合的氨基酸衍生物：其中X和Y独立地为C 1-10二价烃基 ; m为0〜4的整数。 Ra是氢原子，含有1至4个碳原子的一价烃基或由以下通式（2）表示的有机基团：其中R b是氢原子，C 1-7单价烃基，碱金属或 碱土金属，Rc独立地为氢原子，羟基或任选含有氧原子，硫原子或氮原子的C1-10一价烃基）; Z为由通式（2）表示的有机基团。

公开(公告)号：US08338630B2

公开(公告)日：2012-12-25

申请号：US12965203

申请日：2010-12-10

申请人： Hiroyuki Moriya

发明人： Hiroyuki Moriya

IPC分类号： C07F7/18

CPC分类号： C07C227/18 ,  C07C229/26 ,  C07C231/02 ,  C08G77/26 ,  C08G77/388 ,  C07C237/06

摘要： An amino acid-modified organopolysiloxane is provided. It has an amino acid derivative bonded to at least one silicon atom of the organopolysiloxane segment constituting the backbone of the organopolysiloxane via an amide bond represented by the following general formula (1): wherein X and Y are independently a C1-10 divalent hydrocarbon group; m is an integer of 0 to 4; Ra is hydrogen atom, a monovalent hydrocarbon group containing 1 to 4 carbon atoms, or an organic group represented by the following general formula (2): (wherein Rb is hydrogen atom, a C1-7 monovalent hydrocarbon group, an alkaline metal, or an alkaline earth metal, and Rc is independently hydrogen atom, hydroxy group, or a C1-10 monovalent hydrocarbon group optionally containing oxygen atom, sulfur atom, or nitrogen atom); and Z is an organic group represented by the general formula (2).

摘要翻译： 提供氨基酸改性的有机聚硅氧烷。 其具有通过由以下通式（1）表示的酰胺键与构成有机聚硅氧烷的主链的有机聚硅氧烷链段的至少一个硅原子键合的氨基酸衍生物：其中X和Y独立地为C 1-10二价烃基 ; m为0〜4的整数。 Ra是氢原子，含有1至4个碳原子的一价烃基或由以下通式（2）表示的有机基团：其中R b是氢原子，C 1-7单价烃基，碱金属或 碱土金属，Rc独立地为氢原子，羟基或任选含有氧原子，硫原子或氮原子的C1-10一价烃基）; Z为由通式（2）表示的有机基团。

公开(公告)号：US08163807B2

公开(公告)日：2012-04-24

申请号：US12429007

申请日：2009-04-23

申请人： Hideya Katsuhara ,  Hiroyuki Moriya ,  Tomohito Nakajima ,  Kazuya Hongo

发明人： Hideya Katsuhara ,  Hiroyuki Moriya ,  Tomohito Nakajima ,  Kazuya Hongo

IPC分类号： B01F5/06

CPC分类号： B01F3/0807 ,  B01F5/0451 ,  B01F5/0463 ,  B01F13/1013 ,  B01F13/1016

摘要： A blending apparatus is provided, the blending apparatus including: an outer tube; and at least one inner tube disposed inside the outer tube, wherein a distal end, in a lengthwise direction, of the inner tube is located at an intermediate position, in a lengthwise direction, of the outer tube, and the inner tube has plural of through holes in a vicinity of the distal end thereof.

摘要翻译： 提供一种混合装置，所述混合装置包括：外管; 以及设置在所述外管内的至少一个内管，其中，所述内管的长度方向的远端位于所述外管的长度方向的中间位置，所述内管具有多个 通孔在其远端附近。

公开(公告)号：US20060288882A1

公开(公告)日：2006-12-28

申请号：US11367769

申请日：2006-03-03

申请人： Hiroyuki Moriya

发明人： Hiroyuki Moriya

IPC分类号： B30B15/26

CPC分类号： G01L5/0066 ,  G01L1/2268 ,  G01L5/0076 ,  H03M1/10

摘要： The present invention relates to a zero point correction circuit for a load meter used for a press machine or the like, and more particularly to a configuration with which a zero point correction is made a plurality of times after a predetermined amount of time elapses, after press processing is performed, and a zero point correction value is set by calculating an average value of measured values. The predetermined amount of time is measured, for example, with an internal timer or the like, a sampling process is performed after the predetermined amount of time elapses, and an average value of sampled values is calculated and set as a zero point correction value, whereby an accurate zero point correction value can be obtained.

摘要翻译： 本发明涉及一种用于压机等的负载表的零点校正电路，更具体地说，涉及在经过预定时间量之后进行零点校正多次的配置 执行按压处理，并通过计算测量值的平均值来设定零点校正值。 例如，通过内部定时器等来测量预定量的时间，在经过预定时间量之后执行采样处理，并且计算采样值的平均值并将其设置为零点校正值， 从而可以获得精确的零点校正值。

公开(公告)号：US06858497B2

公开(公告)日：2005-02-22

申请号：US10922141

申请日：2004-08-19

申请人： Hiroyuki Moriya ,  Toshio Kobayashi

发明人： Hiroyuki Moriya ,  Toshio Kobayashi

IPC分类号： H01L21/8247 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/115 ,  H01L29/51 ,  H01L29/788 ,  H01L29/792 ,  H01L21/336

CPC分类号： H01L29/513 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/518 ,  H01L29/7923 ,  Y10S257/908

摘要： The present invention prevents production of residue which causes short-circuit between word lines. A memory cell comprises a channel formation region CH, charge storage films CSF each comprised of a plurality of stacked dielectric films, two storages comprised of regions of the charge storage films CSF overlapping the two ends of the channel formation region CH, a single-layer dielectric film DF2 contacting the channel formation region CH between the storages, auxiliary layers (for example, bit lines BL1 and BL2) formed on two impurity regions S/D, two first control electrodes CG1 and CG2 formed on the auxiliary layers with dielectric film interposed and positioned on the storages, and a second control electrode WL buried in a state insulated from the first control electrodes CG1 and CG2 in a space between them and contacting the single-layer dielectric film DF2. Since the main regions on facing surfaces of the first control electrodes CG1 and CG2 become forward tapered, conductive residue is not left at the time of processing the second control electrode WL.

摘要翻译： 本发明防止产生在字线之间短路的残留物。 存储单元包括沟道形成区域CH，每个由多个堆叠的电介质膜组成的电荷存储膜CSF，由与沟道形成区域CH的两端重叠的电荷存储膜CSF的区域组成的两个存储器，单层 电介质膜DF2与存储器之间的沟道形成区域CH，形成在两个杂质区域S / D上的辅助层（例如位线BL1和BL2）接触，形成在辅助层上的两个第一控制电极CG1和CG2， 并且位于存储器上，以及第二控制电极WL，其在与它们之间的空间中与第一控制电极CG1和CG2绝缘的状态下被掩埋并与单层电介质膜DF2接触。 由于第一控制电极CG1和CG2的相对表面上的主要区域向前渐变，所以在处理第二控制电极WL时不会导致残留物。