公开(公告)号：US06323534B1

公开(公告)日：2001-11-27

申请号：US09293192

申请日：1999-04-16

申请人： Kenneth W. Marr ,  Michael P. Violette

发明人： Kenneth W. Marr ,  Michael P. Violette

IPC分类号： H01L2900

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： A metal silicide fuse for a semiconductor device. A conductive region of the fuse may be disposed adjacent a common well of semiconductive material of a first conductivity type. A terminal region of the fuse may be disposed adjacent a well of semiconductive material of a second conductivity type. A narrowed region of the fuse, which is disposed between the terminal region and the conductive region, is disposed adjacent a boundary between the two wells. Upon applying at least a programming current to the fuse, the fuse preferably “blows” at the narrowed region. The diode or diodes between the different conductivity type wells and the Schottky diode or diodes between the remaining portions of the fuse and adjacent wells of the semiconductor device control the flow of current through the remainder of the fuse and through the adjacent conductive wells of the semiconductor device. Thus, if the fuse “blows” as desired, the diodes and Schottky diodes formed by the fuse and the adjacent conductive wells will prevent current at a normal operating voltage from flowing through the conductive wells of the semiconductor device. The present invention also includes methods of fabricating a fuse.

摘要翻译： 一种用于半导体器件的金属硅化物熔断器。 保险丝的导电区域可以邻近第一导电类型的半导体材料的公共孔布置。 保险丝的端子区域可以邻近第二导电类型的半导体材料的孔设置。 设置在端子区域和导电区域之间的保险丝的窄区域邻近两个阱之间的边界设置。 当至少对保险丝施加编程电流时，保险丝优选地在变窄的区域“吹”。 不同导电类型阱之间的二极管或二极管与保险丝的剩余部分和半导体器件的相邻阱之间的肖特基二极管或二极管控制通过保险丝的其余部分的电流的流动并通过半导体的相邻导电阱 设备。 因此，如果熔丝根据需要“吹”，由熔丝和相邻导电阱形成的二极管和肖特基二极管将防止在正常工作电压下的电流流过半导体器件的导电阱。 本发明还包括制造保险丝的方法。

公开(公告)号：US06301148B1

公开(公告)日：2001-10-09

申请号：US09542629

申请日：2000-04-04

申请人： Michael P. Violette

发明人： Michael P. Violette

IPC分类号： G11C1100

CPC分类号： H01L21/76202

摘要： A static random access memory cell comprising a first invertor including a first p-channel pullup transistor, and a first n-channel pulldown transistor in series with the first p-channel pullup transistor; a second invertor including a second p-channel pullup transistor, and a second n-channel pulldown transistor in series with the second n-channel pullup transistor, the first invertor being cross-coupled with the second invertor, the first and second pullup transistors sharing a common active area; a first access transistor having an active terminal connected to the first invertor; a second access transistor having an active terminal connected to the second invertor; and an isolator isolating the first pullup transistor from the second pullup transistor.

摘要翻译： 一种包括第一反相器的静态随机存取存储单元，包括第一p沟道上拉晶体管和与第一p沟道上拉晶体管串联的第一n沟道下拉晶体管; 包括第二p沟道上拉晶体管的第二反相器和与所述第二n沟道上拉晶体管串联的第二n沟道下拉晶体管，所述第一反相器与所述第二反相器交叉耦合，所述第一和第二上拉晶体管共享 一个共同的活跃区域; 第一存取晶体管，具有连接到第一反相器的有源端子; 第二存取晶体管，具有连接到第二反相器的有源端子; 以及将所述第一上拉晶体管与所述第二上拉晶体管隔离的隔离器。

公开(公告)号：US06268292B1

公开(公告)日：2001-07-31

申请号：US09382041

申请日：1999-08-24

申请人： Michael P. Violette ,  Sanh Tang ,  Daniel M. Smith

发明人： Michael P. Violette ,  Sanh Tang ,  Daniel M. Smith

IPC分类号： H01L2144

CPC分类号： H01L21/76855 ,  H01L21/32053 ,  H01L21/32137 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76895

摘要： A method for use in the fabrication of semiconductor devices includes forming a titanium nitride film and depositing a silicon hard mask over the titanium nitride film. The silicon hard mask is used to pattern a titanium nitride interconnect from the titanium nitride film and the silicon hard mask is also used as a contact etch stop for forming a contact area. In forming the interconnect, the silicon hard mask is dry etched stopping selectively on and exposing portions of the titanium nitride film and the exposed portions of the titanium nitride film are etched resulting in the titanium nitride interconnect. In using the silicon hard mask as a contact etch stop, an insulating layer is deposited over the silicon hard mask and the insulating layer is etched using the silicon hard mask as an etch stop to form the contact area. The silicon hard mask is then converted to a metal silicide contact area. Interconnects formed using the method are also described.

摘要翻译： 用于制造半导体器件的方法包括在氮化钛膜上形成氮化钛膜并沉积硅硬掩模。 硅硬掩模用于从氮化钛膜图案化氮化钛互连，并且硅硬掩模也用作用于形成接触区域的接触蚀刻停止。 在形成互连件时，将硅硬掩模干蚀刻选择性地停止并暴露氮化钛膜的部分，并且氮化钛膜的暴露部分被蚀刻，导致氮化钛互连。 在使用硅硬掩模作为接触蚀刻停止件时，在硅硬掩模上沉积绝缘层，并且使用硅硬掩模作为蚀刻停止层来蚀刻绝缘层以形成接触区域。 然后将硅硬掩模转换成金属硅化物接触区域。 还描述了使用该方法形成的互连。

公开(公告)号：US5846873A

公开(公告)日：1998-12-08

申请号：US597586

申请日：1996-02-02

申请人： Michael P. Violette ,  Fernando Gonzalez

发明人： Michael P. Violette ,  Fernando Gonzalez

IPC分类号： H01L21/02 ,  H01L21/033 ,  H01L21/311 ,  H01L21/3205 ,  H01L21/3213 ,  H01L21/768

CPC分类号： H01L21/76831 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/32053 ,  H01L21/32139 ,  H01L21/76895 ,  H01L28/20

摘要： A method of creating ultra-small nibble structures using a modification of an already existing mask includes the steps of depositing a layer of nitride on a circuit being fabricated according to standard MOSFET process steps. A layer of photoresist is patterned using a modification of an existing mask, such as a contact mask modified to include a nibble pattern. The nitride layer and an underlying oxide layer are removed according to the patterned photoresist to create a contact opening and an opening over the field oxide. Spacers may be created in the opening over the field oxide. A conductive layer and a polysilicon layer exposed in the opening over the field oxide are removed extending the opening down to the field oxide to create a nibble structure in the polysilicon layer.

摘要翻译： 使用已经存在的掩模的修改来创建超小型半字节结构的方法包括在根据标准MOSFET工艺步骤制造的电路上沉积氮化物层的步骤。 使用现有掩模的修改，例如修改为包括半字节图案的接触掩模，对光致抗蚀剂层进行图案化。 根据图案化的光致抗蚀剂去除氮化物层和下面的氧化物层，以在场氧化物上形成接触开口和开口。 可以在场氧化物的开口中产生间隔。 去除暴露在场氧化物上的开口中的导电层和多晶硅层，将开口向下延伸到场氧化物，以在多晶硅层中产生半字节结构。

公开(公告)号：US5741735A

公开(公告)日：1998-04-21

申请号：US650286

申请日：1996-05-20

申请人： Michael P. Violette ,  Fernando Gonzalez

发明人： Michael P. Violette ,  Fernando Gonzalez

IPC分类号： H01L21/74 ,  H01L21/768 ,  H01L21/8244 ,  H01L27/11 ,  H01L21/336

CPC分类号： H01L21/743 ,  H01L27/11 ,  H01L27/1104 ,  H01L21/76895 ,  Y10S257/903

摘要： A retrograde well region, having a buried layer of high conductivity, is formed in a semiconductor substrate. A trench structure is selectively etched in the semiconductor substrate down to a region proximate to or within the buried layer. A conducting local interconnect material is formed within and proximate to the trench structure to electrically connect surface portions of the substrate to the buried layer. The buried layer is used to provide a voltage source to an integrated circuit. In one application, a P-type buried layer provides ground potential or V.sub.SS to a source region of an N-channel FET transistor. In a second application, an N-type buried layer provides supply potential or V.sub.CC to a source of a P-channel FET transistor.

摘要翻译： 在半导体衬底中形成具有高导电性掩埋层的逆行阱区。 沟槽结构在半导体衬底中被选择性地蚀刻到靠近或在掩埋层内的区域。 导电性局部互连材料形成在沟槽结构内部和附近，以将衬底的表面部分电连接到掩埋层。 掩埋层用于向集成电路提供电压源。 在一个应用中，P型埋层向N沟道FET晶体管的源极区提供接地电位或VSS。 在第二个应用中，N型掩埋层向P沟道FET晶体管的源极提供电源电位或VCC。

公开(公告)号：US5358884A

公开(公告)日：1994-10-25

申请号：US943840

申请日：1992-09-11

申请人： Michael P. Violette

发明人： Michael P. Violette

IPC分类号： H01L21/331 ,  H01L21/74 ,  H01L21/763 ,  H01L29/417 ,  H01L21/265

CPC分类号： H01L29/66272 ,  H01L21/743 ,  H01L21/763 ,  H01L29/41708 ,  Y10S148/01

摘要： A scheme and method of fabrication for creating bipolar semiconductor devices with reduced size and greater speed while maintaining device isolation. Using a mesa structure isolated by trenches, collector contact is achieved by a vertical layer of polysilicon surrounding the mesa, deposited within the trench during fabrication.

摘要翻译： 一种用于在保持器件隔离的同时制造具有减小尺寸和更大速度的双极半导体器件的制造方案和方法。 使用由沟槽隔离的台面结构，通过在制造期间沉积在沟槽内的跨越台阶的垂直多晶硅层实现集电极接触。

公开(公告)号：US08809108B2

公开(公告)日：2014-08-19

申请号：US12950827

申请日：2010-11-19

申请人： Jun Liu ,  Michael P. Violette

发明人： Jun Liu ,  Michael P. Violette

IPC分类号： H01L21/00 ,  H01L45/00

CPC分类号： H01L45/06 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/1253 ,  H01L45/143 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1608 ,  H01L45/1675 ,  H01L45/1683

摘要： Some embodiments include methods of forming memory cells. Such methods can include forming a first electrode, a second electrode, and a memory element directly contacting the first and second electrodes. Forming the memory element can include forming a programmable portion of the memory element isolated from the first electrode by a first portion of the memory element and isolated from the second electrode by a second portion of the memory element. Other embodiments are described.

摘要翻译： 一些实施例包括形成存储器单元的方法。 这样的方法可以包括形成第一电极，第二电极和直接接触第一和第二电极的存储元件。 存储元件的形成可以包括通过存储元件的第一部分形成与第一电极隔离的存储元件的可编程部分，并通过存储元件的第二部分与第二电极隔离。 描述其他实施例。

公开(公告)号：US07816246B2

公开(公告)日：2010-10-19

申请号：US11499134

申请日：2006-08-03

申请人： Zhongze Wang ,  Michael P. Violette ,  Jigish Trivedi

发明人： Zhongze Wang ,  Michael P. Violette ,  Jigish Trivedi

IPC分类号： H01L21/8234 ,  H01L21/44

CPC分类号： H01L21/76888 ,  H01L23/5256 ,  H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

摘要： Fuses for integrated circuits and semiconductor devices and methods for using the same. The semiconductor fuse contains two conductive layers, an overlying and underlying refractory metal nitride layer, on an insulating substrate. The semiconductor fuse may be fabricated during manufacture of a local interconnect structure including the same materials. The fuse, which may be used to program redundant circuitry, may be blown by electrical current rather than laser beams, thus allowing the fuse width to be smaller than prior art fuses blown by laser beams. The fuse may also be blown by less electrical current than the current required to blow conventional polysilicon fuses having similar dimensions.

摘要翻译： 用于集成电路和半导体器件的保险丝及其使用方法。 半导体熔丝在绝缘基板上包含两层导电层，一层覆盖和下层的难熔金属氮化物层。 可以在制造包括相同材料的局部互连结构的过程中制造半导体熔丝。 可以用于编程冗余电路的保险丝可以由电流而不是激光束吹扫，从而允许熔丝宽度小于由激光束熔断的现有技术的熔丝。 熔断器也可能被吹过比吹出具有相似尺寸的常规多晶硅保险丝所需的电流更小的电流。

公开(公告)号：US20090231910A1

公开(公告)日：2009-09-17

申请号：US12046307

申请日：2008-03-11

申请人： Jun Liu ,  Michael P. Violette

发明人： Jun Liu ,  Michael P. Violette

IPC分类号： H01L21/06

CPC分类号： H01L45/143 ,  H01L27/2409 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/142 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/16 ,  H01L45/1675

摘要： Some embodiments include apparatus and methods having a memory element configured to store information and an access component configured to allow conduction of current through the memory element when a first voltage difference in a first direction across the memory element and the access component exceeds a first voltage value and to prevent conduction of current through the memory element when a second voltage difference in a second direction across the memory element and the access component exceeds a second voltage value, wherein the access component includes a material excluding silicon.

摘要翻译： 一些实施例包括具有被配置为存储信息的存储器元件的设备和方法以及被配置为当存储元件和存取组件之间的第一方向上的第一电压差超过第一电压值时允许通过存储元件的电流的导通 并且当所述存储元件和所述存取组件之间的第二方向上的第二电压差超过第二电压值时，防止通过所述存储元件的电流传导，其中所述存取组件包括不包括硅的材料。

公开(公告)号：US07118950B2

公开(公告)日：2006-10-10

申请号：US11000588

申请日：2004-11-30

申请人： Sanh D. Tang ,  Michael P. Violette ,  Robert Burke

发明人： Sanh D. Tang ,  Michael P. Violette ,  Robert Burke

IPC分类号： H01L21/336

CPC分类号： H01L29/7833 ,  G06K19/0723 ,  G06K19/0726 ,  G06K19/07771 ,  H01L21/76229 ,  H01L21/76232 ,  H01L21/76264 ,  H01L21/823418 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/823814 ,  H01L21/823828 ,  H01L29/1083 ,  H01L29/41783 ,  H01L29/66545 ,  H01L29/66583 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834

摘要： In one implementation, a method of forming a field effect transistor includes etching an opening into source/drain area of a semiconductor substrate. The opening has a base comprising semiconductive material. After the etching, insulative material is formed within the opening over the semiconductive material base. The insulative material less than completely fills the opening and has a substantially uniform thickness across the opening. Semiconductive source/drain material is formed within the opening over the insulative material within the opening. A transistor gate is provided operatively proximate the semiconductive source/drain material. Other aspects and implementations are contemplated.