公开(公告)号：US20200152472A1

公开(公告)日：2020-05-14

申请号：US16674790

申请日：2019-11-05

Applicant: Tokyo Electron Limited

Inventor： Anton DEVILLIERS ,  Robert BRANDT ,  Jeffrey SMITH ,  Jodi GRZESKOWIAK ,  Daniel FULFORD

IPC: H01L21/3105 ,  H01L21/027 ,  G03F7/004 ,  G03F7/09 ,  G03F7/38 ,  G03F7/16 ,  G03F7/32 ,  G03F7/20

Abstract: Techniques herein include methods for planarizing films including films used in the fabrication of semiconductor devices. Such fabrication can generate structures on a surface of a substrate, and these structures can have a spatially variable density across the surface. Planarization methods herein include depositing a first acid-labile film overtop the structures and the substrate, the first acid-labile film filling between the structures. A second acid-labile film is deposited overtop the first acid-labile film. An acid source film is deposited overtop the second acid-labile film, the acid source film including an acid generator configured to generate an acid in response to receiving radiation having a predetermined wavelength of light. A pattern of radiation is projected over the acid source film, the pattern of radiation having a spatially variable intensity at predetermined areas of the pattern of radiation.

公开(公告)号：US20250123090A1

公开(公告)日：2025-04-17

申请号：US18485762

申请日：2023-10-12

Applicant: Tokyo Electron Limited

Inventor： Daniel FULFORD ,  Mark I. GARDNER ,  Henry Jim FULFORD ,  Anton DEVILLIERS

IPC: G01B7/28

Abstract: An apparatus for measuring bow of a wafer, includes a substrate holder having a support surface configured to support a wafer; and a capacitor array unit including a plurality of electrodes laterally spaced from one another in the capacitor array unit. Each electrode faces the support surface and is spaced a respective fixed distance from the support surface such that each electrode can form a capacitor with an opposing area of a substrate provided on the support surface of the substrate holder.

公开(公告)号：US20210242351A1

公开(公告)日：2021-08-05

申请号：US17074125

申请日：2020-10-19

Applicant: Tokyo Electron Limited

Inventor： MARK I. GARDNER ,  H. Jim FULFORD ,  Anton DEVILLIERS

IPC: H01L29/792 ,  H01L27/11578 ,  H01L27/092

Abstract: A charge trap field-effect transistor (FET) includes multiple layers of dielectric material defining a charge trapping layer. A p-doped (or n-doped) source region and a p-doped (or n-doped) drain region are connected via a nano-channel, the nano-channel being formed between the multiple layers of dielectric, thus forming a charge trap FET. A charge trap complimentary current field-effect transistor (CFET) includes multiple layers of dielectric material defining a charge trapping layer and includes a 3D charge trap PFET formed with p+ symmetrical source/drain region formed over a 3D charge trap NFET formed with n+ symmetrical source/drain region.

公开(公告)号：US20210166975A1

公开(公告)日：2021-06-03

申请号：US16848213

申请日：2020-04-14

Applicant: Tokyo Electron Limited

Inventor： Mark I. GARDNER ,  H. Jim FULFORD ,  Anton DEVILLIERS

IPC: H01L21/768 ,  H01L21/822 ,  H01L21/306 ,  H01L23/48 ,  H01L23/532

Abstract: Techniques herein include methods for fabricating three-dimensional (3D) logic or memory stack integrated with 3D metal routing. The methods can include stacking metal layers within existing 3D silicon stacks. A first portion can be masked while a second, uncovered portion is etched. Predetermined layers in a bottom portion (disposed closer to the substrate) of the multilayer stack can be replaced with a conductor. The second portion can be masked while the first portion is uncovered and processed. This can enable higher density 3D circuits by having multiple metal lines contained within a multilayer 3D nano-sheet. Advantageously, this facilitates easier connections for 3D logic and memory. Moreover, better speed performance can be achieved by having reduced distance for signals to travel to transistor connections.

公开(公告)号：US20210098294A1

公开(公告)日：2021-04-01

申请号：US17034930

申请日：2020-09-28

Applicant: Tokyo Electron Limited

Inventor： Jeffrey SMITH ,  Lars LIEBMANN ,  Daniel CHANEMOUGAME ,  Hiroki NIIMI ,  Kandabara TAPILY ,  Subhadeep KAL ,  Jodi GRZESKOWIAK ,  Anton DEVILLIERS

IPC: H01L21/768 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/8234 ,  H01L29/66

Abstract: A method of fabricating a semiconductor device is provided. The method includes forming BPR structures filled with a replacement BPR material, first S/D structures, first replacement silicide layers, and a pre-metallization dielectric that covers the first replacement silicide layers and the first S/D structures. The method also includes forming first interconnect openings in the pre-metallization dielectric and first replacement interconnect layers in the first interconnect openings. The first replacement interconnect layers are connected to the first replacement silicide layers. A thermal process is executed. The method further includes replacing, from a first side of the first wafer, a first group of the first replacement interconnect layers, a first group of the first replacement silicide layers, and the replacement BPR material, and replacing, from a second side of the first wafer, a second group of the first replacement interconnect layers, and a second group of the first replacement silicide layers.

公开(公告)号：US20210088907A1

公开(公告)日：2021-03-25

申请号：US17032980

申请日：2020-09-25

Applicant: Tokyo Electron Limited

Inventor： Jodi GRZESKOWIAK ,  Anthony SCHEPIS ,  Anton DEVILLIERS

IPC: G03F7/09 ,  H01L21/027 ,  H01L21/3065 ,  H01L21/308 ,  G03F7/11 ,  G03F7/004

Abstract: A method for patterning a substrate in which a patterned photoresist structure can be formed on the substrate, the patterned photoresist structure having a sidewall. A conformal layer of spacer material can be deposited on the sidewall. The patterned photoresist structure can then be removed from the substrate, leaving behind the spacer material. Then, the substrate can be directionally etched using the sidewall spacer as an etch mask to form the substrate having a target critical dimension.