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    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
    11.
    发明申请
    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 有权
    半导体集成电路设备

    公开(公告)号：US20100066419A1

    公开(公告)日：2010-03-18

    申请号：US12554570

    申请日：2009-09-04

    申请人： Mototsugu Hamada ,  Tsuyoshi Nishikawa ,  Toshiyuki Furusawa

    发明人： Mototsugu Hamada ,  Tsuyoshi Nishikawa ,  Toshiyuki Furusawa

    IPC分类号： H03L7/00

    CPC分类号： H03K19/17736 ,  H03K19/1736 ,  H03K19/17728 ,  H03K19/1778

    摘要： A semiconductor integrated circuit device has a combinational logic circuit including one or plural logic cells connected in series. At least one of the logic cells includes a standard cell which includes a MIS transistor, an input terminal to which an output signal from a previous stage is inputted as an input signal, and an output terminal. A first conductivity-type first MIS transistor which is provided between the output terminal of the standard cell and a first power supply voltage, the first MIS transistor including a control terminal to which a circuit control signal is inputted, and the first MIS transistor supplying the first power supply voltage to the output terminal of the standard cell based on the circuit control signal in order to bring the standard cell into an operation-stopped state. A second conductivity-type second MIS transistor cuts off a leakage current of the MIS transistor in the standard cell.

    摘要翻译： 半导体集成电路器件具有包括串联连接的一个或多个逻辑单元的组合逻辑电路。 逻辑单元中的至少一个包括标准单元，其包括MIS晶体管，作为输入信号输入来自前一级的输出信号的输入端子和输出端子。 第一导电型第一MIS晶体管，设置在标准单元的输出端子与第一电源电压之间，第一MIS晶体管包括输入电路控制信号的控制端子，以及第一MIS晶体管， 基于电路控制信号向标准单元的输出端子提供第一电源电压，以使标准单元进入操作停止状态。 第二导电型第二MIS晶体管截止在标准单元中的MIS晶体管的漏电流。

    Semiconductor integrated circuit device
    12.
    发明授权
    Semiconductor integrated circuit device 失效
    半导体集成电路器件

    公开(公告)号：US07602211B2

    公开(公告)日：2009-10-13

    申请号：US12132428

    申请日：2008-06-03

    申请人： Mototsugu Hamada ,  Tsuyoshi Nishikawa ,  Toshiyuki Furusawa

    发明人： Mototsugu Hamada ,  Tsuyoshi Nishikawa ,  Toshiyuki Furusawa

    IPC分类号： H03K17/16 ,  H03K19/003

    CPC分类号： H03K19/17736 ,  H03K19/1736 ,  H03K19/17728 ,  H03K19/1778

    摘要： A semiconductor integrated circuit device has a combinational logic circuit including one or plural logic cells connected in series. At least one of the logic cells includes a standard cell which includes a MIS transistor, an input terminal to which an output signal from a previous stage is inputted as an input signal, and an output terminal. A first conductivity-type first MIS transistor which is provided between the output terminal of the standard cell and a first power supply voltage, the first MIS transistor including a control terminal to which a circuit control signal is inputted, and the first MIS transistor supplying the first power supply voltage to the output terminal of the standard cell based on the circuit control signal in order to bring the standard cell into an operation-stopped state. A second conductivity-type second MIS transistor cuts off a leakage current of the MIS transistor in the standard cell.

    摘要翻译： 半导体集成电路器件具有包括串联连接的一个或多个逻辑单元的组合逻辑电路。 逻辑单元中的至少一个包括标准单元，其包括MIS晶体管，作为输入信号输入来自前一级的输出信号的输入端子和输出端子。 第一导电型第一MIS晶体管，设置在标准单元的输出端子与第一电源电压之间，第一MIS晶体管包括输入电路控制信号的控制端子，以及第一MIS晶体管， 基于电路控制信号向标准单元的输出端子提供第一电源电压，以使标准单元进入操作停止状态。 第二导电型第二MIS晶体管截止在标准单元中的MIS晶体管的漏电流。

    Semiconductor integrated circuit, logic operation circuit, and flip flop
    14.
    发明授权
    Semiconductor integrated circuit, logic operation circuit, and flip flop 失效
    半导体集成电路，逻辑运算电路和触发器

    公开(公告)号：US06750680B2

    公开(公告)日：2004-06-15

    申请号：US09883959

    申请日：2001-06-20

    申请人： Hidemasa Zama ,  Masayuki Koizumi ,  Yukiko Ito ,  Kimiyoshi Usami ,  Naoyuki Kawabe ,  Masahiro Kanazawa ,  Toshiyuki Furusawa

    发明人： Hidemasa Zama ,  Masayuki Koizumi ,  Yukiko Ito ,  Kimiyoshi Usami ,  Naoyuki Kawabe ,  Masahiro Kanazawa ,  Toshiyuki Furusawa

    IPC分类号： H03K19096

    CPC分类号： H03K19/01707 ,  H03K19/0016

    摘要： There is provided a semiconductor integrated circuit, a logic operation circuit and a flip flop capable of operating at a high speed and having a leak electric current reduced. In a semiconductor integrated circuit according to the present invention, only a gate circuit on a critical path is constituted by an MT gate cell obtained by combining transistors having a low threshold voltage with transistors having a high threshold voltage, and any other gate circuit is constituted by a transistor having a high threshold voltage. Consequently, the gate circuit on the critical path can be operated at a high speed, and the overall leak electric current can be suppressed, thereby reducing the consumption power.

    摘要翻译： 提供了能够高速运行并且具有泄漏电流降低的半导体集成电路，逻辑运算电路和触发器。在根据本发明的半导体集成电路中，仅在关键路径上的门电路 由具有低阈值电压的晶体管与具有高阈值电压的晶体管组合而获得的MT门单元构成，并且任何其它门电路由具有高阈值电压的晶体管构成。 因此，关键路径上的门电路可以高速运转，能够抑制整体的漏电流，从而降低功耗。

    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
    16.
    发明申请
    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
    半导体集成电路设备

    公开(公告)号：US20080238485A1

    公开(公告)日：2008-10-02

    申请号：US12132428

    申请日：2008-06-03

    申请人： Mototsugu HAMADA ,  Tsuyoshi Nishikawa ,  Toshiyuki Furusawa

    发明人： Mototsugu HAMADA ,  Tsuyoshi Nishikawa ,  Toshiyuki Furusawa

    IPC分类号： H03K19/096

    CPC分类号： H03K19/17736 ,  H03K19/1736 ,  H03K19/17728 ,  H03K19/1778

    摘要： A semiconductor integrated circuit device has a combinational logic circuit including one or plural logic cells connected in series. At least one of the logic cells includes a standard cell which includes a MIS transistor, an input terminal to which an output signal from a previous stage is inputted as an input signal, and an output terminal. A first conductivity-type first MIS transistor which is provided between the output terminal of the standard cell and a first power supply voltage, the first MIS transistor including a control terminal to which a circuit control signal is inputted, and the first MIS transistor supplying the first power supply voltage to the output terminal of the standard cell based on the circuit control signal in order to bring the standard cell into an operation-stopped state. A second conductivity-type second MIS transistor cuts off a leakage current of the MIS transistor in the standard cell.

    摘要翻译： 半导体集成电路器件具有包括串联连接的一个或多个逻辑单元的组合逻辑电路。 逻辑单元中的至少一个包括标准单元，其包括MIS晶体管，作为输入信号输入来自前一级的输出信号的输入端子和输出端子。 第一导电型第一MIS晶体管，设置在标准单元的输出端子与第一电源电压之间，第一MIS晶体管包括输入电路控制信号的控制端子，以及第一MIS晶体管， 基于电路控制信号向标准单元的输出端子提供第一电源电压，以使标准单元进入操作停止状态。 第二导电型第二MIS晶体管截止在标准单元中的MIS晶体管的漏电流。

    Digital arithmetic integrated circuit
    19.
    发明授权
    Digital arithmetic integrated circuit 失效
    数字运算集成电路

    公开(公告)号：US06643677B2

    公开(公告)日：2003-11-04

    申请号：US09503080

    申请日：2000-02-14

    申请人： Toshiyuki Furusawa ,  Yusei Itaya ,  Masaru Ozeki

    发明人： Toshiyuki Furusawa ,  Yusei Itaya ,  Masaru Ozeki

    IPC分类号： G06F738

    CPC分类号： G06F7/5443

    摘要： A digital signal processor (DSP) of high speed and high precision is disclosed. The DSP (i.e., digital arithmetic integrated circuit) comprises: an arithmetic data storing memory (11) for storing arithmetic data and for outputting, in one instruction cycle, first and second arithmetic data strings each composed of a plurality of bits, the first arithmetic data string being composed of m-bits of at least a predetermined unit word length and the second arithmetic data string being composed of (m×n)-bits of a unit word length; two arithmetic operand storing registers (12) for storing the first and second arithmetic data strings outputted by said arithmetic data storing memory, respectively; an arithmetic logical unit for executing arithmetic operation on the basis of the two operands outputted by said arithmetic operand storing registers in one instruction cycle (13); and an arithmetic result storing register (15) for storing the arithmetic results outputted by said arithmetic logical unit.

    摘要翻译： 公开了一种高速，高精度的数字信号处理器（DSP）。 DSP（即，数字运算集成电路）包括：运算数据存储存储器，用于存储运算数据，并在一个指令周期内输出由多个位组成的第一和第二运算数据串，第一运算 数据串由至少预定单位字长的m位构成，第二算术数据串由单位字长度的（m×n）位构成; 两个算术运算存储寄存器（12），用于分别存储由所述算术数据存储存储器输出的第一和第二算术数据串; 算术逻辑单元，用于在一个指令周期（13）中基于由所述算术运算存储寄存器输出的两个操作数执行算术运算; 以及用于存储由所述算术逻辑单元输出的算术结果的算术结果存储寄存器（15）。

    Digital signal processor and processor reducing the number of instructions upon processing condition execution instructions
    20.
    发明授权
    Digital signal processor and processor reducing the number of instructions upon processing condition execution instructions 失效
    数字信号处理器和处理器在处理条件执行指令时减少指令数量

    公开(公告)号：US06427205B1

    公开(公告)日：2002-07-30

    申请号：US09342266

    申请日：1999-06-29

    申请人： Koichi Mori ,  Toshiyuki Furusawa ,  Daisuke Sonoda

    发明人： Koichi Mori ,  Toshiyuki Furusawa ,  Daisuke Sonoda

    IPC分类号： G06F938

    CPC分类号： G06F9/3867 ,  G06F9/3842

    摘要： In a digital signal processor for pipeline processing divided into at least three steps, i.e., instruction fetch cycle, instruction decode cycle and instruction execution cycle, a value of a register (A) is put on a data bus assuming the condition is consistent when a condition execution instruction is decoded in an instruction decoder (14). Then, in the instruction execution cycle of the condition execution instruction, a register (B) introduced the value on the data bus when upon consistency of the condition. As a result, even before a condition flag (Z) changes as a result of execution of the instruction for generating the condition in the instruction execution cycle, the condition execution instruction can be decoded. Thus, the processor may omit an instruction other than “condition generation instruction or condition execution instruction” which was conventionally required.

    摘要翻译： 在用于流水线处理的数字信号处理器中，分为至少三个步骤，即指令提取周期，指令解码周期和指令执行周期，寄存器（A）的值放在数据总线上，假设条件是一致的，当a 条件执行指令在指令解码器（14）中解码。 然后，在条件执行指令的指令执行周期中，当条件一致时，寄存器（B）将该值引入数据总线上。 结果，即使在条件标志（Z）作为执行用于在指令执行周期中生成条件的指令的结果而变化的情况下，可以对条件执行指令进行解码。 因此，处理器可以省略除常规要求的“条件生成指令或条件执行指令”之外的指令。