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40 条记录 (耗时 0.032 秒)

    Clock generation circuit for analog value memory circuit
    12.
    发明授权
    Clock generation circuit for analog value memory circuit 失效
    模拟值存储电路的时钟发生电路

    公开(公告)号：US5999462A

    公开(公告)日：1999-12-07

    申请号：US205200

    申请日：1998-12-04

    申请人： Masayuki Katakura ,  Masashi Takeda

    发明人： Masayuki Katakura ,  Masashi Takeda

    IPC分类号： G11C7/22 ,  G11C27/04 ,  G11C7/00

    CPC分类号： G11C7/222 ,  G11C27/04 ,  G11C7/22

    摘要： An analog delay circuit which includes an analog memory circuit wherein a plurality of memory cells each including a memory capacitor and a selection switch for the memory capacitor are arranged in a matrix includes row switches provided for the individual columns for individually being driven by row selection signals. A same clock signal from a clock generation circuit is supplied commonly to an X direction scanning circuit and a Y direction scanning circuit. The number of stages of registers of the X direction scanning circuit and the number of stages of registers of the Y direction scanning circuit are set so that they have no common divisor other than 1. Consequently, when the memory cells are to be selectively scanned, a same selection condition can be provided to all of the memory cells without relying upon the positions of the memory cells, and the parasitic capacitance connected to a signal write/read terminal is reduced.

    摘要翻译： 一种包括模拟存储电路的模拟延迟电路，其中包括存储电容器和用于存储电容器的选择开关的多个存储单元被布置成矩阵，包括为各个列提供的行开关，用于单独由行选择信号驱动 。 来自时钟发生电路的相同时钟信号被共同地提供给X方向扫描电路和Y方向扫描电路。 将X方向扫描电路的寄存器的级数和Y方向扫描电路的寄存器的级数设置为除了1以外没有公共除数。因此，当要选择性地扫描存储器单元时， 可以在不依赖于存储单元的位置的情况下向所有存储单元提供相同的选择条件，并且减少连接到信号写/读终端的寄生电容。

    Digital-to-analog converting system
    14.
    发明授权
    Digital-to-analog converting system 失效
    数模转换系统

    公开(公告)号：US4739304A

    公开(公告)日：1988-04-19

    申请号：US917308

    申请日：1986-10-10

    申请人： Masashi Takeda ,  Ikuro Hata ,  Masayuki Katakura ,  Norio Shoji

    发明人： Masashi Takeda ,  Ikuro Hata ,  Masayuki Katakura ,  Norio Shoji

    IPC分类号： H03M1/00 ,  H03M1/68 ,  H03M1/82

    CPC分类号： H03M1/68 ,  H03M1/745 ,  H03M1/822

    摘要： A digital-to-analog convertor divides an input digital signal into a least significant bit group and a most significant bit group. The most significant bit group is converted using pulse amplitude modulation and the least significant bit group is converted using pulse width modulation, in which the pulse widths are varied symmetrically about predetermined time points within a conversion period in order to improve the linearity of the pulse width modulation conversion.

    摘要翻译： 数模转换器将输入数字信号分为最低有效位组和最高有效位组。 使用脉冲幅度调制转换最高有效位组，并且使用脉冲宽度调制转换最低有效位组，其中脉冲宽度在转换周期内关于预定时间点对称地改变，以便提高脉冲宽度的线性 调制转换。

    Peak detector having signal rise-time enhancement
    15.
    发明授权
    Peak detector having signal rise-time enhancement 失效
    峰值检测器具有信号上升时间增强

    公开(公告)号：US3999125A

    公开(公告)日：1976-12-21

    申请号：US570359

    申请日：1975-04-22

    申请人： Masashi Takeda ,  Atsushi Matsuzaki

    发明人： Masashi Takeda ,  Atsushi Matsuzaki

    IPC分类号： G01R19/00 ,  G01R19/04 ,  G01R19/16

    CPC分类号： G01R19/04

    摘要： A peak detector having rise-time enhancement of input signals is comprised of a feedback amplifier including two input terminals and a feedback circuit which interconnects the amplifier output terminal with one of the input terminals; and a peak detecting circuit, including a capacitor, coupled to the other of the amplifier input terminals. The capacitor voltage is applied as an input signal to the feedback amplifier, and abrupt changes in the rise-time portion of the input signals are detected and are used to vary the amplifier feedback so as to enhance the output signal produced by the amplifier during the rise-time portion.

    摘要翻译： 具有输入信号的上升时间增强的峰值检测器由包括两个输入端的反馈放大器和将放大器输出端与其中一个输入端互连的反馈电路构成; 以及包括耦合到放大器输入端子中的另一个的电容器的峰值检测电路。 将电容器电压作为输入信号施加到反馈放大器，并且检测输入信号的上升时间部分的突然变化，并用于改变放大器反馈，以便增强在放大器期间产生的输出信号 上升时间部分。

    Capsule Room Unit And Two-Level Installation Structure Thereof
    16.
    发明申请
    Capsule Room Unit And Two-Level Installation Structure Thereof 有权
    胶囊室单位及其两级安装结构

    公开(公告)号：US20110000146A1

    公开(公告)日：2011-01-06

    申请号：US12881874

    申请日：2010-09-14

    申请人： Masashi Takeda ,  Masakuni Takeda

    发明人： Masashi Takeda ,  Masakuni Takeda

    IPC分类号： E04H1/02 ,  E04C2/20

    CPC分类号： E04H3/02 ,  A47C29/003 ,  A61G7/0526 ,  E04B1/3483 ,  E04B1/5825 ,  E04B1/5831 ,  E04B2001/405 ,  E04H1/125 ,  F16B7/187

    摘要： A capsule room unit for use as a capsule bed or other private space has a horizontally oblong rectangular parallelepiped room framework formed by columns, beams and panel materials fitted into the room framework to constitute a ceiling, a floor and walls, wherein the columns and the beams are composed of extruded materials each having a longitudinally consecutive groove. The panel materials of the ceiling and walls are composed of synthetic resin or FRP hollow panel materials each having peripheral flanges at a periphery along a plane direction, and the flanges of the hollow panel material are inserted and fitted to the grooves of the extruded materials.

    摘要翻译： 用作胶囊床或其他私人空间的胶囊室单元具有由柱，梁和面板材料形成的水平方形长方体的平行六面体框架，该框架安装在房间框架中以构成天花板，地板和墙壁，其中柱和 梁由挤压材料组成，各自具有纵向连续的凹槽。 天花板和墙壁的面板材料由合成树脂或FRP中空板材料组成，每个板材沿着平面方向在周边具有周边凸缘，并且中空板材料的凸缘插入并装配到挤压材料的槽中。

    Latched comparator circuit
    19.
    发明授权
    Latched comparator circuit 失效
    锁存比较器电路

    公开(公告)号：US4559522A

    公开(公告)日：1985-12-17

    申请号：US564203

    申请日：1983-12-22

    申请人： Takeo Sekino ,  Masashi Takeda

    发明人： Takeo Sekino ,  Masashi Takeda

    IPC分类号： H03K3/2885 ,  H03M1/00 ,  H03K13/175

    CPC分类号： H03K3/2885 ,  H03M1/1245

    摘要： A latched comparator circuit is disclosed in which a voltage comparator circuit of a differential construction composing a part of the latched comparator circuit is substituted for by a plurality of differential amplifying circuits connected in parallel to the prior stage thereof and which are supplied with a differential input. Also, there is disclosed a latched comparator circuit in which a voltage comparator circuit of a differential construction composing a part of the latched comparator circuit is substituted for by a plurality of differential amplifying circuits connected in parallel to the prior stage thereof that are supplied with a differential input for voltage comparison and in which a switching circuit is provided between the differential amplifying circuits and a latch circuit for electrically separating both of them upon latch operation.

    摘要翻译： 一种锁存比较器电路，其中构成锁存比较器电路的一部分的差分结构的电压比较器电路由与其前级并联连接的多个差分放大电路代替，并被提供有差分输入 。 此外，公开了一种锁存比较器电路，其中构成锁存比较器电路的一部分的差分结构的电压比较器电路由与其前级并联连接的多个差分放大电路代替，所述差分放大电路被提供有 用于电压比较的差分输入，并且其中在差分放大电路之间提供开关电路和用于在锁存操作时将它们两者电分离的锁存电路。

    Digital-to-analog converter
    20.
    发明授权
    Digital-to-analog converter 失效
    数模转换器

    公开(公告)号：US4404546A

    公开(公告)日：1983-09-13

    申请号：US329698

    申请日：1981-12-11

    申请人： Ikuro Hata ,  Masashi Takeda

    发明人： Ikuro Hata ,  Masashi Takeda

    IPC分类号： H03M1/82 ,  H03M1/00 ,  H03M1/66 ,  H03K13/02

    CPC分类号： H03M1/82

    摘要： An integrating digital-to-analog converter circuit includes an operational-amplifier based integrator, a plurality of constant current sources each providing constant current at a respective different level, and a plurality of switches each associated with a respective current source for coupling the same to the integrator. A plurality of digital counters are arranged to hold a predetermined portion of an n-bit digital word loaded therein and to count clock pulses until their contents reach a predetermined count. At those times, a carry pulse is generated in each such digital counter and the associated switch is opened to cut off the associated current source. Such a digital-to-analog converter circuit can convert data words of relatively high bit length without the need for an excessively high frequency clocking signal.

    摘要翻译： 集成数模转换器电路包括基于运算放大器的积分器，每个在各个不同电平上提供恒定电流的多个恒定电流源，以及多个开关，每个开关各自与相应的电流源相关联，以将其耦合到 集成商。 多个数字计数器被布置为保持加载在其中的n位数字字的预定部分，并且对时钟脉冲进行计数，直到其内容达到预定计数。 在这些时间，在每个这样的数字计数器中产生进位脉冲，并且打开关联的开关以切断相关联的电流源。 这样的数模转换器电路可以转换相对较高位长度的数据字，而不需要过高的频率时钟信号。