公开(公告)号：US10446489B2

公开(公告)日：2019-10-15

申请号：US16170059

申请日：2018-10-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ko-Wei Lin ,  Hung-Miao Lin ,  Chun-Ling Lin ,  Ying-Lien Chen ,  Huei-Ru Tsai ,  Sheng-Yi Su

IPC: H01L23/528 ,  H01L21/285 ,  H01L21/768 ,  H01L23/532 ,  H01L23/522

Abstract: An interconnect structure includes a dielectric layer and a conductor embedded in the dielectric layer. A top surface of the conductor is flush with a top surface of the dielectric layer. A cobalt cap layer is deposited on the top surface of the conductor. A nitrogen-doped cobalt layer is disposed on the cobalt cap layer.

公开(公告)号：US10323332B2

公开(公告)日：2019-06-18

申请号：US15206321

申请日：2016-07-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Ling Lin ,  Yen-Liang Lu ,  Chi-Mao Hsu ,  Chin-Fu Lin ,  Chun-Hung Chen ,  Tsun-Min Cheng ,  Chi-Ray Tsai

IPC: C25D7/12 ,  C25D5/00 ,  C25D3/38 ,  C25D5/10 ,  C25D5/54 ,  H01L21/288 ,  H01L21/768

Abstract: An electrical chemical plating process is provided. A semiconductor structure is provided in an electrical plating platform. A pre-electrical-plating step is performed wherein the pre-electrical-plating step is carried out under a fixed voltage environment and lasts for 0.2 to 0.5 seconds after the current is above the threshold current of the electrical plating platform. After the pre-electrical-plating step, a first electrical plating step is performed on the semiconductor structure.

公开(公告)号：US20160319450A1

公开(公告)日：2016-11-03

申请号：US15206321

申请日：2016-07-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Ling Lin ,  Yen-Liang Lu ,  Chi-Mao Hsu ,  Chin-Fu Lin ,  Chun-Hung Chen ,  Tsun-Min Cheng ,  Chi-Ray Tsai

IPC: C25D5/54 ,  H01L21/768 ,  C25D7/12 ,  H01L21/288 ,  C25D3/38 ,  C25D5/10

CPC classification number: C25D5/54 ,  C25D3/38 ,  C25D5/00 ,  C25D5/10 ,  C25D7/123 ,  H01L21/2885 ,  H01L21/76879

Abstract: An electrical chemical plating process is provided. A semiconductor structure is provided in an electrical plating platform. A pre-electrical-plating step is performed wherein the pre-electrical-plating step is carried out under a fixed voltage environment and lasts for 0.2 to 0.5 seconds after the current is above the threshold current of the electrical plating platform. After the pre-electrical-plating step, a first electrical plating step is performed on the semiconductor structure.

Abstract translation: 提供电化学镀工艺。 半导体结构设置在电镀平台中。 进行预电镀步骤，其中预电镀步骤在固定电压环境下进行，并且在电流高于电镀平台的阈值电流之后持续0.2至0.5秒。 在预电镀步骤之后，对半导体结构进行第一电镀步骤。

公开(公告)号：US20250159916A1

公开(公告)日：2025-05-15

申请号：US19019409

申请日：2025-01-13

Applicant: UNITED MICROELECTRONICS CORP,

Inventor： Ko-Wei Lin ,  Chun-Chieh Chiu ,  Chun-Ling Lin ,  Shu Min Huang ,  Hsin-Fu Huang

IPC: H10D30/01 ,  H01L21/324 ,  H01L21/768 ,  H10D30/47 ,  H10D62/85

Abstract: A high electron mobility transistor includes a channel layer disposed on a substrate, a barrier layer disposed on the channel layer, a gate structure disposed on the barrier layer, a source contact structure and a drain contact structure disposed on the barrier layer at two sides of the gate structure, and extending through the barrier layer to directly contact the channel layer, and a gate contact structure disposed on the gate structure. The source contact structure, the drain contact structure, and the gate contact structure respectively include a liner and a metal layer directly disposed on the liner. The metal layer comprises a metal material doped with a first additive, and a weight percentage of the first additive in the metal layer is between 0% and 2%.

公开(公告)号：US20190067184A1

公开(公告)日：2019-02-28

申请号：US16170059

申请日：2018-10-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ko-Wei Lin ,  Hung-Miao Lin ,  Chun-Ling Lin ,  Ying-Lien Chen ,  Huei-Ru Tsai ,  Sheng-Yi Su

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/532 ,  H01L21/285

CPC classification number: H01L23/528 ,  H01L21/28556 ,  H01L21/28562 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76856 ,  H01L21/76871 ,  H01L23/5226 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53295

Abstract: An interconnect structure includes a dielectric layer and a conductor embedded in the dielectric layer. A top surface of the conductor is flush with a top surface of the dielectric layer. A cobalt cap layer is deposited on the top surface of the conductor. A nitrogen-doped cobalt layer is disposed on the cobalt cap layer.

公开(公告)号：US10079177B1

公开(公告)日：2018-09-18

申请号：US15694354

申请日：2017-09-01

Applicant: United Microelectronics Corp.

Inventor： Ko-Wei Lin ,  Ying-Lien Chen ,  Chun-Ling Lin ,  Huei-Ru Tsai ,  Hung-Miao Lin ,  Sheng-Yi Su ,  Tzu-Hao Liu

IPC: H01L21/44 ,  H01L21/768 ,  H01L21/288

CPC classification number: H01L21/76873 ,  H01L21/28556 ,  H01L21/288 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76847 ,  H01L21/76862 ,  H01L23/53238

Abstract: A method is provided for forming copper material over a substrate. The method includes forming a barrier layer over a substrate. Then, a depositing-soaking-treatment (DST) process is performed over the barrier layer. A copper layer is formed on the cobalt layer. The DST process includes depositing a cobalt layer on the barrier layer. Then, the cobalt layer is soaked with H2 gas at a first pressure. The cobalt layer is treated with a H2 plasma at a second pressure. The second pressure is lower than the first pressure.

公开(公告)号：US20180261537A1

公开(公告)日：2018-09-13

申请号：US15466847

申请日：2017-03-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ko-Wei Lin ,  Hung-Miao Lin ,  Chun-Ling Lin ,  Ying-Lien Chen ,  Huei-Ru Tsai ,  Sheng-Yi Su

IPC: H01L23/528 ,  H01L23/532 ,  H01L21/285 ,  H01L21/768

CPC classification number: H01L23/528 ,  H01L21/28556 ,  H01L21/76871 ,  H01L23/5226 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53295

Abstract: An interconnect structure includes a dielectric layer and a conductor embedded in the dielectric layer. A top surface of the conductor is flush with a top surface of the dielectric layer. A cobalt cap layer is deposited on the top surface of the conductor. A nitrogen-doped cobalt layer is disposed on the cobalt cap layer.

公开(公告)号：US20150340280A1

公开(公告)日：2015-11-26

申请号：US14817227

申请日：2015-08-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jia-Jia Chen ,  Chi-Mao Hsu ,  Tsun-Min Cheng ,  Chun-Ling Lin ,  Huei-Ru Tsai ,  Ching-Wei Hsu ,  Chin-Fu Lin ,  Hsin-Yu Chen

IPC: H01L21/768

CPC classification number: H01L21/76847 ,  H01L21/76898 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A through silicon via structure is located in a recess of a substrate. The through silicon via structure includes a barrier layer, a buffer layer and a conductive layer. The barrier layer covers a surface of the recess. The buffer layer covers the barrier layer. The conductive layer is located on the buffer layer and fills the recess, wherein the contact surface between the conductive layer and the buffer layer is smoother than the contact surface between the buffer layer and the barrier layer. Moreover, a through silicon via process forming said through silicon via structure is also provided.

Abstract translation: 硅通孔结构位于衬底的凹槽中。 贯通硅通孔结构包括阻挡层，缓冲层和导电层。 阻挡层覆盖凹部的表面。 缓冲层覆盖阻挡层。 导电层位于缓冲层上并填充凹槽，其中导电层和缓冲层之间的接触表面比缓冲层和阻挡层之间的接触表面更平滑。 此外，还提供了形成所述贯穿硅通孔结构的通硅通孔工艺。

公开(公告)号：US08598033B1

公开(公告)日：2013-12-03

申请号：US13646726

申请日：2012-10-07

Applicant: United Microelectronics Corp.

Inventor： Kuo-Chih Lai ,  Chia Chang Hsu ,  Bor-Shyang Liao ,  Chun-Ling Lin ,  Shu Min Huang ,  Min-Chung Cheng ,  Chi-Mao Hsu

IPC: H01L21/4763

CPC classification number: H01L21/28518 ,  H01L21/76843 ,  H01L21/76855

Abstract: The present invention provides a method for forming a salicide layer. First, a metal-atom-containing layer is formed on a substrate, a first rapid thermal process (RTP) is then performed to the metal-atom-containing layer to form a transitional salicide layer on a specific region. The metal-atom-containing layer is then removed, a thermal conductive layer is formed on the surface of the transitional salicide layer, and a second RTP is performed on the transitional salicide layer.

Abstract translation: 本发明提供一种形成硅化物层的方法。 首先，在基板上形成含有金属原子的层，然后对含金属原子的层进行第一快速热处理（RTP），以在特定区域形成过渡型硅化物层。 然后除去含金属原子的层，在过渡型自对准硅化物层的表面上形成导热层，在过渡型硅化物层上进行第二层RTP。