中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

18 records (took 0.014 seconds)

    TRANSISTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
    12.
    发明公开
    TRANSISTOR STRUCTURE AND MANUFACTURING METHOD THEREOF 审中-公开

    公开(公告)号：US20230335609A1

    公开(公告)日：2023-10-19

    申请号：US17736071

    申请日：2022-05-03

    Applicant: United Microelectronics Corp.

    Inventor： Ming-Hua Tsai ,  Wei Hsuan Chang ,  Chin-Chia Kuo

    IPC: H01L29/423 ,  H01L29/40 ,  H01L21/8234

    CPC classification number: H01L29/42368 ,  H01L29/401 ,  H01L21/823462 ,  H01L27/088

    Abstract: The invention provides a transistor structure and a manufacturing method thereof. The transistor structure includes a substrate, a first gate, a second gate, a first gate dielectric layer, and a second gate dielectric layer. The first gate and the second gate are located on the substrate. The first gate dielectric layer is located between the first gate and the substrate. The first gate dielectric layer has a single thickness. The second gate dielectric layer is located between the second gate and the substrate. The second gate dielectric layer has a plurality of thicknesses. A maximum thickness of the first gate dielectric layer is the same as a maximum thickness of the second gate dielectric layer. The transistor structure may reduce process complexity.

    HIGH-VOLTAGE TRANSISTOR, LEVEL-UP SHIFTING CIRCUIT, AND SEMICONDUCTOR DEVICE
    14.
    发明公开
    HIGH-VOLTAGE TRANSISTOR, LEVEL-UP SHIFTING CIRCUIT, AND SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20240222455A1

    公开(公告)日：2024-07-04

    申请号：US18107516

    申请日：2023-02-09

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Wei-Hsuan Chang ,  Ming-Hua Tsai ,  Chin-Chia Kuo

    IPC: H01L29/423 ,  H01L27/088 ,  H01L29/10 ,  H01L29/78

    CPC classification number: H01L29/42368 ,  H01L27/088 ,  H01L29/1066 ,  H01L29/7816 ,  H01L29/41725

    Abstract: A high-voltage transistor includes a well region disposed in a semiconductor substrate, a gate structure disposed above the well region, a gate oxide layer disposed between the gate structure and the well region, a first drift region, and a second drift region. A first portion of the gate oxide layer is thicker than a second portion of the gate oxide layer. A thickness of the second portion is greater than or equal to one eighth of a thickness of the first portion. The first drift region and the second drift region are disposed in the well region, at least partially located at two opposite sides of the gate structure, respectively, and disposed adjacent to the first portion and the second portion, respectively. A conductivity type of the first drift region is identical to that of the second drift region. A level-up shifting circuit includes the high-voltage transistor described above.

    Semiconductor structure
    15.
    发明申请
    Semiconductor structure 有权

    公开(公告)号：US20230006062A1

    公开(公告)日：2023-01-05

    申请号：US17366053

    申请日：2021-07-02

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Wei-Hsuan Chang ,  Ming-Hua Tsai ,  Chin-Chia Kuo

    IPC: H01L29/78 ,  H01L29/45

    Abstract: A semiconductor structure is provided, and the semiconductor structure includes a substrate, and an active area is defined thereon, a gate structure spanning the active area, wherein the overlapping range of the gate structure and the active area is defined as an overlapping region, and the overlapping region includes four corners, and at least one salicide block covering the four corners of the overlapping region.

    SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF
    17.
    发明申请
    SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF 有权

    公开(公告)号：US20250015161A1

    公开(公告)日：2025-01-09

    申请号：US18237420

    申请日：2023-08-24

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Wei-Hsuan Chang ,  Ming-Hua Tsai ,  Chin-Chia Kuo

    IPC: H01L29/66 ,  H01L21/285 ,  H01L29/423 ,  H01L29/45 ,  H01L29/78

    Abstract: A semiconductor device includes a substrate; a channel region disposed in the substrate; and a diffusion region disposed in the substrate on a side of the channel region. The diffusion region comprises a LDD region and a heavily doped region within the LDD region. A gate electrode is disposed over the channel region. The gate electrode partially overlaps with the LDD region. A spacer is disposed on a sidewall of the gate electrode. A gate oxide layer is disposed between the gate electrode and the channel region, between the gate electrode and the LDD region, and between the spacer and the LDD region. A silicide layer is disposed on the heavily doped region and is spaced apart from the edge of the spacer.

Patent Agency Ranking