公开(公告)号：US10056288B1

公开(公告)日：2018-08-21

申请号：US15672272

申请日：2017-08-08

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Tsuo-Wen Lu ,  Chin-Wei Wu ,  Tien-Chen Chan ,  Ger-Pin Lin ,  Shu-Yen Chan

IPC: H01L21/762 ,  H01L21/8234 ,  H01L27/108 ,  H01L29/423 ,  H01L21/764 ,  H01L21/02

CPC classification number: H01L21/76237 ,  H01L21/02164 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/764 ,  H01L21/823481 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10891 ,  H01L29/4236

Abstract: A semiconductor device includes a semiconductor substrate having a gate trench penetrating through an active area and a trench isolation region surrounding the active area. The gate trench exposes a sidewall of the active area and a sidewall of the trench isolation region. The sidewall of the trench isolation region includes a void. A first gate dielectric layer conformally covers the sidewall of the active area and the sidewall of the trench isolation region. The void in the sidewall of the trench isolation region is filled with the first gate dielectric layer. A second gate dielectric layer is grown on the sidewall of the active area. A gate is embedded in the gate trench.

公开(公告)号：US20180226470A1

公开(公告)日：2018-08-09

申请号：US15873913

申请日：2018-01-18

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Ger-Pin Lin ,  Tien-Chen Chan ,  Shu-Yen Chan ,  Chi-Mao Hsu ,  Shih-Fang Tzou

IPC: H01L49/02 ,  H01L27/108

CPC classification number: H01L28/84 ,  H01L27/10808 ,  H01L27/10852 ,  H01L28/90 ,  H01L28/91

Abstract: A method of fabricating a bottom electrode includes providing a dielectric layer. An atomic layer deposition is performed to form a bottom electrode material on the dielectric layer. Then, an oxidation process is performed to oxidize part of the bottom electrode material. The oxidized bottom electrode material transforms into an oxide layer. The bottom electrode material which is not oxidized becomes a bottom electrode. A top surface of the bottom electrode includes numerous hill-like profiles. Finally, the oxide layer is removed.

公开(公告)号：US09680022B1

公开(公告)日：2017-06-13

申请号：US15207916

申请日：2016-07-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tien-Chen Chan ,  Yi-Fan Li ,  Yen-Hsing Chen ,  Chun-Yu Chen ,  Chung-Ting Huang ,  Zih-Hsuan Huang ,  Ming-Hua Chang ,  Yu-Shu Lin ,  Shu-Yen Chan

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/06 ,  H01L21/02 ,  H01L29/66 ,  H01L29/08 ,  H01L29/161

CPC classification number: H01L29/66795 ,  H01L21/02532 ,  H01L21/0262 ,  H01L29/1054 ,  H01L29/66636 ,  H01L29/7848 ,  H01L29/785

Abstract: A semiconductor device is provided, including a substrate with an isolation layer formed thereon, wherein the substrate has a fin protruding up through the isolation layer to form a top surface and a pair of lateral sidewalls of the fin above the isolation layer; a silicon-germanium (SiGe) layer epitaxially grown on the top surface and the lateral sidewalls of the fin; and a gate stack formed on the isolation layer and across the fin, wherein the fin and the gate stack respectively extend along a first direction and a second direction. The SiGe layer formed on the top surface has a first thickness, the SiGe layer formed on said lateral sidewall has a second thickness, and a ratio of the first thickness to the second thickness is in a range of 1:10 to 1:30.

公开(公告)号：US20130288446A1

公开(公告)日：2013-10-31

申请号：US13928366

申请日：2013-06-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ted Ming-Lang Guo ,  Chin-Cheng Chien ,  Shu-Yen Chan ,  Ling-Chun Chou ,  Tsung-Hung Chang ,  Chun-Yuan Wu

IPC: H01L29/66

CPC classification number: H01L29/66477 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/7843 ,  H01L29/7847

Abstract: A semiconductor structure including a substrate and a gate structure disposed on the substrate is disclosed. The gate structure includes a gate dielectric layer disposed on the substrate, a gate material layer disposed on the gate dielectric layer and an outer spacer with a rectangular cross section. The top surface of the outer spacer is lower than the top surface of the gate material layer.

Abstract translation: 公开了一种包括衬底和设置在衬底上的栅极结构的半导体结构。 栅极结构包括设置在基板上的栅极介质层，设置在栅极介电层上的栅极材料层和具有矩形横截面的外部间隔物。 外隔离物的顶表面比栅极材料层的顶表面低。

公开(公告)号：US10608093B2

公开(公告)日：2020-03-31

申请号：US15873904

申请日：2018-01-18

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Chia-Wei Wu ,  Ting-Pang Chung ,  Tien-Chen Chan ,  Shu-Yen Chan

IPC: H01L29/423 ,  H01L27/108 ,  H01L27/12 ,  H01L21/02 ,  H01L29/49 ,  H01L29/08 ,  H01L29/06 ,  H01L27/11568 ,  H01L27/11578

Abstract: A semiconductor device and a method of forming the same are disclosed. First, a substrate having a main surface is provided. At least a trench is formed in the substrate. A barrier layer is formed in the trench and a conductive material is formed on the barrier layer and filling up the trench. The barrier layer and the conductive material are then recessed to be lower than the upper surface of the substrate. After that, an oxidation process is performed to oxidize the barrier layer and the conductive material thereby forming an insulating layer.

公开(公告)号：US10217750B1

公开(公告)日：2019-02-26

申请号：US15712133

申请日：2017-09-21

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Ger-Pin Lin ,  Kuan-Chun Lin ,  Chi-Mao Hsu ,  Shu-Yen Chan ,  Shih-Fang Tzou ,  Tsuo-Wen Lu ,  Tien-Chen Chan ,  Feng-Yi Chang ,  Shih-Kuei Yen ,  Fu-Che Lee

IPC: H01L27/108 ,  H01L21/28

Abstract: A method of fabricating a buried word line structure includes providing a substrate with a word line trench therein. Two source/drain doped regions are disposed in the substrate at two sides of the word line trench. Later, a silicon oxide layer is formed to cover the word line trench. A titanium nitride layer is formed to cover the silicon oxide layer. Next, a tilt ion implantation process is performed to implant silicon atoms into the titanium nitride layer to transform part of the titanium nitride layer into a titanium silicon nitride layer. A conductive layer is formed in the word line trench. Subsequently, part of the conductive layer, part of the titanium silicon nitride layer and part of the silicon oxide layer are removed to form a recess. Finally, a cap layer fills in the recess.

公开(公告)号：US20180197868A1

公开(公告)日：2018-07-12

申请号：US15866482

申请日：2018-01-10

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Ger-Pin Lin ,  Tien-Chen Chan ,  Shu-Yen Chan ,  Yung-Ming Wang ,  Chien-Ting Ho

IPC: H01L27/108 ,  H01L21/76 ,  H01L21/02 ,  H01L21/3115

CPC classification number: H01L27/10891 ,  H01L21/02164 ,  H01L21/31155 ,  H01L21/76 ,  H01L21/76224 ,  H01L21/76237

Abstract: A semiconductor device and a manufacturing method thereof include providing a substrate including an active region of a conductivity type and an isolation structure, in which the isolation structure surrounds the active region; forming a word line trench on the substrate, the word line trench intersecting the active region; and forming two doped regions in the active region at two sides of the word line trench respectively, in which each doped region and a bottom surface of the word line trench are located in a same level, and each doped region includes dopants of the conductivity type or an intrinsic semiconductor dopants.

公开(公告)号：US20180190771A1

公开(公告)日：2018-07-05

申请号：US15854769

申请日：2017-12-27

Applicant: United Microelectronics Corp. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Ger-Pin Lin ,  Tien-Chen Chan ,  Shu-Yen Chan

IPC: H01L29/08 ,  H01L27/108 ,  H01L29/167 ,  H01L23/535 ,  H01L21/265 ,  H01L21/223

CPC classification number: H01L29/0847 ,  H01L21/2236 ,  H01L21/26513 ,  H01L23/535 ,  H01L27/10814 ,  H01L27/1082 ,  H01L27/10823 ,  H01L27/10855 ,  H01L27/10867 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10891 ,  H01L29/167

Abstract: The present invention provides a semiconductor structure, the semiconductor structure includes a substrate, at least one active area is defined on the substrate, a buried word line is disposed in the substrate, a source/drain region disposed beside the buried word line, a diffusion barrier region, disposed at the top of the source/drain region, the diffusion barrier region comprises a plurality of doping atoms selected from the group consisting of carbon atoms, nitrogen atoms, germanium atoms, oxygen atoms, helium atoms and xenon atoms, a dielectric layer disposed on the substrate, and a contact structure disposed in the dielectric layer, and electrically connected to the source/drain region.

公开(公告)号：US20130256701A1

公开(公告)日：2013-10-03

申请号：US13905148

申请日：2013-05-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chan-Lon Yang ,  Ted Ming-Lang Guo ,  Chin-I Liao ,  Chin-Cheng Chien ,  Shu-Yen Chan ,  Chun-Yuan Wu

IPC: H01L29/78

CPC classification number: H01L29/7848 ,  H01L21/30608 ,  H01L21/3247 ,  H01L21/823425 ,  H01L29/6656 ,  H01L29/66636

Abstract: A strained silicon channel semiconductor structure comprises a substrate having an upper surface, a gate structure formed on the upper surface, at least one recess formed in the substrate at lateral sides of the gate structure, wherein the recess has at least one sidewall which has an upper sidewall and a lower sidewall concaved in the direction to the gate structure, and the included angle between the upper sidewall and horizontal plane ranges between 54.5°-90°, and an epitaxial layer filled into the two recesses.

Abstract translation: 应变硅沟道半导体结构包括具有上表面的衬底，形成在上表面上的栅极结构，在栅极结构的侧面处形成在衬底中的至少一个凹部，其中凹部具有至少一个侧壁，其具有 上侧壁和下侧壁在与栅极结构的方向上凹陷，并且上侧壁和水平面之间的夹角在54.5°-90°之间，并且填充到两个凹部中的外延层。

公开(公告)号：US20230189498A1

公开(公告)日：2023-06-15

申请号：US18106448

申请日：2023-02-06

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Luo-Hsin Lee ,  Ting-Pang Chung ,  Shih-Han Hung ,  Po-Han Wu ,  Shu-Yen Chan ,  Shih-Fang Tzou

IPC: H10B12/00

CPC classification number: H10B12/0387 ,  H01L28/60 ,  H10B12/37 ,  H10B12/0335 ,  H10B12/315

Abstract: A method of forming a semiconductor device includes the following steps. First of all, a substrate is provided, and a dielectric layer is formed on the substrate. Then, at least one trench is formed in the dielectric layer, to partially expose a top surface of the substrate. The trench includes a discontinuous sidewall having a turning portion. Next, a first deposition process is performed, to deposit a first semiconductor layer to fill up the trench and to further cover on the top surface of the dielectric layer. Following these, the first semiconductor layer is laterally etched, to partially remove the first semiconductor layer till exposing the turning portion of the trench. Finally, a second deposition is performed, to deposit a second semiconductor layer to fill up the trench.