公开(公告)号：US11508783B2

公开(公告)日：2022-11-22

申请号：US17235785

申请日：2021-04-20

Applicant: United Microelectronics Corp.

Inventor： Chung-Tse Chen ,  Ko-Chi Chen ,  Tzu-Yun Chang

IPC: H01L27/24 ,  H01L45/00

Abstract: A method for fabricating memory device is provided. The method includes forming a transistor on a substrate. Further, a contact structure is formed on a source/drain region of the transistor. A conductive layer is formed on the contact structure. Four memory structures are formed on the conductive layer to form a quadrilateral structure.

公开(公告)号：US20200083344A1

公开(公告)日：2020-03-12

申请号：US16123868

申请日：2018-09-06

Applicant: United Microelectronics Corp.

Inventor： Hsueh-Chun Hsiao ,  Tzu-Yun Chang ,  Chuan-Fu Wang ,  Yu-Huang Yeh

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  H01L29/49 ,  H01L29/45

Abstract: A memory structure including a substrate, a first gate structure, a second gate structure, a first spacer, a second spacer, and a third spacer is provided. The first gate structure includes a first gate and a charge storage layer. The charge storage layer is disposed between the first gate and the substrate. The second gate structure is disposed on the substrate. The second gate structure includes a second gate. A height of the first gate is higher than a height of the second gate. The first spacer and the second spacer are respectively disposed on one sidewall and the other sidewall of the first gate structure. The first spacer is located between the first gate structure and the second gate structure. The third spacer is disposed on a sidewall of the first spacer and covers a portion of a top surface of the second gate.

公开(公告)号：US20180175110A1

公开(公告)日：2018-06-21

申请号：US15884827

申请日：2018-01-31

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wen-Hsin Hsu ,  Ko-Chi Chen ,  Tzu-Yun Chang

IPC: H01L27/24 ,  H01L45/00 ,  H01L23/528

CPC classification number: H01L27/2463 ,  H01L23/528 ,  H01L27/2436 ,  H01L45/08 ,  H01L45/1226 ,  H01L45/1246 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/147 ,  H01L45/16 ,  H01L45/1608 ,  H05K999/99

Abstract: A semiconductor structure includes a memory unit structure. The memory unit structure includes a transistor, a first electrode, two second electrode, and two resistive random access memory (RRAM) elements. The first electrode and the two second electrodes are disposed in a horizontal plane. The first electrode is disposed between the two second electrodes. The first electrode and the two second electrodes are disposed in parallel. The first electrode is coupled to a source region of the transistor. One of the two RRAM elements is disposed between the first electrode and one of the two second electrodes. The other one of the two RRAM elements is disposed between the first electrode and the other one of the two second electrodes.

公开(公告)号：US12272397B2

公开(公告)日：2025-04-08

申请号：US18180864

申请日：2023-03-09

Applicant: United Microelectronics Corp.

Inventor： Yi Ting Hung ,  Ko-Chi Chen ,  Tzu-Yun Chang

IPC: G11C11/00 ,  G11C13/00

Abstract: A forming operation method of a resistive random access memory is provided. The method includes the following steps. A positive pulse and a negative pulse are sequentially applied, by a bit line/source line driver, to multiple resistive random access memory cells in a direction form a farthest location to a nearest location based on the bit line/source line driver through a bit line and a source line to break down a dielectric film of each of the resistive random access memory cells and generate a conductive filament of each of the resistive random access memory cells.

公开(公告)号：US20240395929A1

公开(公告)日：2024-11-28

申请号：US18337396

申请日：2023-06-19

Applicant: United Microelectronics Corp.

Inventor： Chen-Yuan Lin ,  Yu-Cheng Lo ,  Tzu-Yun Chang

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66

Abstract: A semiconductor device includes a gate structure, a first doped region, a second doped region, an isolation structure, an insulating layer and a field plate. The gate structure is located on a substrate. The first doped region and the second doped region are located at two sides of the gate structure. The isolation structure is located in the substrate between the first doped region and the second doped region, and is separated from the gate structure by a non-zero distance. The insulating layer extends continuously from a portion of a top surface of the gate structure to a portion of a top surface of the isolation structure. The field plate is located on the insulating layer and has the same potential as the gate structure.

公开(公告)号：US20240312527A1

公开(公告)日：2024-09-19

申请号：US18677836

申请日：2024-05-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Ning Peng ,  Hsueh-Chun Hsiao ,  Tzu-Yun Chang

IPC: G11C16/24 ,  G11C16/08 ,  H01L29/788 ,  H10B41/10 ,  H10B41/27

CPC classification number: G11C16/24 ,  G11C16/08 ,  H01L29/7881 ,  H10B41/10 ,  H10B41/27

Abstract: A method for forming semiconductor structure with wave shaped erase gate, the method including the steps: forming a floating gate having staggered islands on a substrate, forming a erase gate having a wave shape on the substrate at a first side of the floating gate, and forming a word line having the wave shape on the substrate at a second side of the floating gate opposite to the first side.

公开(公告)号：US20240282371A1

公开(公告)日：2024-08-22

申请号：US18180864

申请日：2023-03-09

Applicant: United Microelectronics Corp.

Inventor： Yi Ting Hung ,  Ko-Chi Chen ,  Tzu-Yun Chang

IPC: G11C13/00

CPC classification number: G11C13/0026 ,  G11C13/0028 ,  G11C13/0038 ,  G11C13/004 ,  G11C2013/0045

Abstract: A forming operation method of a resistive random access memory is provided. The method includes the following steps. A positive pulse and a negative pulse are sequentially applied, by a bit line/source line driver, to multiple resistive random access memory cells in a direction form a farthest location to a nearest location based on the bit line/source line driver through a bit line and a source line to break down a dielectric film of each of the resistive random access memory cells and generate a conductive filament of each of the resistive random access memory cells.

公开(公告)号：US20220293679A1

公开(公告)日：2022-09-15

申请号：US17224140

申请日：2021-04-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wen-Hsin Hsu ,  Ko-Chi Chen ,  Tzu-Yun Chang ,  Chung-Tse Chen

IPC: H01L27/24 ,  H01L45/00

Abstract: A semiconductor memory device includes a substrate, a dielectric layer on the substrate, and a contact plug in the dielectric layer. An upper portion of the contact plug protrudes from a top surface of the dielectric layer. The upper portion of the contact plug acts as a first electrode. A buffer layer is disposed on the dielectric layer and beside the upper portion of the contact plug. A resistive-switching layer is disposed beside the buffer layer. A second electrode is disposed beside the resistive-switching layer.

公开(公告)号：US20150115461A1

公开(公告)日：2015-04-30

申请号：US14066845

申请日：2013-10-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Chou Yu ,  Hsueh-Chun Hsiao ,  Tzu-Yun Chang

IPC: H01L23/538 ,  H01L21/768

CPC classification number: H01L21/76898 ,  H01L21/8221 ,  H01L23/544 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/0688 ,  H01L2223/54493 ,  H01L2224/9202 ,  H01L2225/06541 ,  H01L2225/06593 ,  H01L2225/06596

Abstract: A semiconductor structure and a method for forming the same are provided. The method includes following steps. A first wafer is provided, which includes a first region, a second region, and a first semiconductor device disposed in the first region. No semiconductor device is disposed in the second region. A second wafer is provided, which includes a third region, a fourth region and a second semiconductor device disposed in the third region. No semiconductor device is disposed in the fourth region. The first region of the first wafer is overlapped with the fourth region of the second wafer. The second region of the first wafer is overlapped with the third region of the second wafer. A first conductive through via is formed to pass through the fourth region of the second wafer and the first region of the first wafer to electrically connect to the first semiconductor device.

Abstract translation: 提供半导体结构及其形成方法。 该方法包括以下步骤。 提供第一晶片，其包括第一区域，第二区域和设置在第一区域中的第一半导体器件。 在第二区域中不设置半导体器件。 提供第二晶片，其包括设置在第三区域中的第三区域，第四区域和第二半导体器件。 在第四区域中不设置半导体器件。 第一晶片的第一区域与第二晶片的第四区域重叠。 第一晶片的第二区域与第二晶片的第三区域重叠。 形成第一导电通孔以通过第二晶片的第四区域和第一晶片的第一区域以电连接到第一半导体器件。

公开(公告)号：US12082405B2

公开(公告)日：2024-09-03

申请号：US18203054

申请日：2023-05-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsueh-Chun Hsiao ,  Yi-Ning Peng ,  Tzu-Yun Chang

IPC: H10B41/30 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/788

CPC classification number: H10B41/30 ,  H01L29/40114 ,  H01L29/42328 ,  H01L29/66492 ,  H01L29/66545 ,  H01L29/66825 ,  H01L29/7833 ,  H01L29/7881

Abstract: An array of programmable memory includes a first floating gate and a second floating gate disposed on a substrate along a first direction, two spacers disposed between and parallel to the first floating gate and the second floating gate, a first word line sandwiched by one of the spacers and the adjacent first floating gate, and a second word line sandwiched by the other one of the spacers and the adjacent second floating gate, and two first spacers disposed on the substrate, wherein one of the first spacer is disposed between the first word line and the first floating gate, and another spacer is disposed between the second word line and the second floating gate, wherein each spacer has substantially the same shape as each first spacer.