公开(公告)号：US20200235231A1

公开(公告)日：2020-07-23

申请号：US16601609

申请日：2019-10-15

Applicant: University of Electronic Science and Technology of China

Inventor： Zehong LI ,  Xin PENG ,  Yishang ZHAO ,  Min REN ,  Bo ZHANG

IPC: H01L29/739 ,  H01L29/423 ,  H01L29/10

Abstract: The present invention relates to the technical field of power semiconductor devices, particularly to an insulated gate bipolar transistor with a MOS controllable hole path. According to the present invention, a MOS controllable gate structure formed by a gate dielectric layer, a MOS control gate electrode and a P-type MOS channel region are embedded in a P+ floating p-body region of the conventional IGBT structure. The MOS region is equivalent to a switch controlled by a gate voltage. When the device is turned on under a forward voltage, the potential of the p-body region is floated to store holes, reducing the saturation conduction voltage drop of the device. Under the condition of turn-off and short-circuit, the hole extracting path is provided and the Miller capacitance is lowered, thereby lowering the turn-off losses and enhancing the short-circuit withstand capability.

公开(公告)号：US20200052687A1

公开(公告)日：2020-02-13

申请号：US16455803

申请日：2019-06-28

Applicant: University of Electronic Science and Technology of China

Inventor： Xin MING ,  Li HU ,  Xuan ZHANG ,  Su PAN ,  Chunqi ZHANG ,  Yao QIN ,  Zhiwen ZHANG ,  Yangli XIN ,  Zhuo WANG ,  Bo ZHANG

IPC: H03K17/06 ,  H03K17/16

Abstract: A switch bootstrap charging circuit suitable for a gate drive circuit of a GaN power device includes a high-voltage MOSFET, a low-voltage MOSFET, a high-voltage MOSFET control module, and a low-voltage MOSFET control module. The low-voltage MOSFET is a PMOS transistor, and the source of the low-voltage MOSFET is connected to the power supply voltage. The drain of the high-voltage MOSFET serves as an output terminal of the switch bootstrap charging circuit. The low-voltage MOSFET control module and the high-voltage MOSFET control module generate a gate drive signal of the low-voltage MOSFET and a gate drive signal of the high-voltage MOSFET according to the gate drive signal of the lower power transistor.

公开(公告)号：US20190371937A1

公开(公告)日：2019-12-05

申请号：US15774291

申请日：2016-09-17

Applicant: University of Electronic Science and Technology of China

Inventor： Min REN ,  Yuci LIN ,  Chi XIE ,  Zhiheng SU ,  Zehong LI ,  Jinping ZHANG ,  Wei GAO ,  Bo ZHANG

IPC: H01L29/78 ,  H01L29/423

Abstract: A trench MOS device with improved single event burnout endurance, applied in the field of semiconductor. The device is provided, in an epitaxial layer, with a conductive type semiconductor pillar connected to a source and a second conductive type current-directing region. Whereby. the trajectory of the electron-hole pairs induced by the single event effect is changed and thus avoids the single event burnout caused by the triggering of parasitic transistors, therefore improving the endurance of the single event burnout of the trench MOS device.

公开(公告)号：US20190067415A1

公开(公告)日：2019-02-28

申请号：US15774286

申请日：2016-09-17

Applicant: University of Electronic Science and Technology of China

Inventor： Min REN ,  Yumeng ZHANG ,  Cong DI ,  Jingzhi XIONG ,  Zehong LI ,  Jinping ZHANG ,  Wei GAO ,  Bo ZHANG

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/40

CPC classification number: H01L29/0615 ,  H01L29/0638 ,  H01L29/407 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7823

Abstract: A junction termination with an internal field plate, the field plate structure and the junction termination extension region are folded inside the device to make full use of the thickness of the drift region in the body, thereby reducing the area of the termination and relieving the electric field concentration at the end of the PN junction. The breakdown position is transferred from the surface into the body of the original PN junction, and the withstand voltage of termination can reach to the breakdown voltage of the parallel plane junction. Under such design, a smaller area can be obtained than that of the conventional structure at the same withstand voltage.

公开(公告)号：US20190036214A1

公开(公告)日：2019-01-31

申请号：US15959305

申请日：2018-04-23

Applicant: University of Electronic Science and Technology of China

Inventor： Yujian CHENG ,  Yichen ZHONG ,  Renbo HE ,  Yan LIU ,  Yong FAN ,  Kaijun SONG ,  Bo ZHANG ,  Xianqi LIN ,  Yonghong ZHANG

IPC: H01Q3/30 ,  H01Q19/06 ,  H01Q13/02 ,  H01Q3/14

Abstract: An antenna for generating an arbitrarily directed Bessel beam, including a beam-forming plane and a feeding horn, the beam-forming plane is a dual-layer dielectric substrate structure having a beam focusing function, including: a printed circuit bottom layer, a high-frequency dielectric substrate lower layer, a printed circuit middle layer, a high-frequency dielectric substrate upper layer, and, a printed circuit upper layer; the printed circuit bottom layer, the high-frequency dielectric substrate lower layer, the printed circuit middle layer, the high-frequency dielectric substrate upper layer, and the printed circuit upper layer are co-axially stacked from the bottom to the top: the beam-forming plane is entirely divided into periodically arranged beam-forming units by a plurality of meshes, and each beam-forming unit consists of printed circuit upper, middle and lower metal patches of which centers are on the same longitudinal axis, the high-frequency dielectric substrate lower layer and the high-frequency dielectric substrate upper layer.

公开(公告)号：US20140304572A1

公开(公告)日：2014-10-09

申请号：US13929758

申请日：2013-06-27

Applicant: University of Electronic Science and Technology of China

Inventor： Yajuan HE ,  Tingting XIA ,  Tao LUO ,  Wubing GAN ,  Bo ZHANG

IPC: G06F11/25

CPC classification number: G01R31/317 ,  G06F1/3243 ,  G06F1/3296 ,  G06F9/3869 ,  Y02D10/152 ,  Y02D10/172

Abstract: A pipelined processor including a combinational logic of several stages, a voltage regulator, a counter, a comparator, and a plurality of stage registers. Each stage register is disposed between two adjacent stages of the combinational logic. The stage register includes a flip-flop, a latch, an XOR gate, and a MUX module. When the high level of a register clock is coming, the flip-flop latches first data at the rising edge, and the latch receives second data during the high level. The data latched by the flip-flop and the latch respectively are compared by the XOR gate. If they are same, the output Error of the XOR gate is low level, and the output of the flip-flop is delivered to the next stage. Otherwise, the output Error of the XOR gate is high level, and the output of the latch is delivered to the next stage.

Abstract translation: 一种流水线处理器，包括几级的组合逻辑，电压调节器，计数器，比较器和多个级寄存器。 每个级寄存器被布置在组合逻辑的两个相邻级之间。 级寄存器包括触发器，锁存器，异或门和MUX模块。 当寄存器时钟的高电平到来时，触发器在上升沿锁存第一数据，并且锁存器在高电平期间接收第二数据。 由触发器和锁存器锁存的数据分别由XOR门进行比较。 如果它们相同，则XOR门的输出误差为低电平，触发器的输出被传送到下一级。 否则，异或门的输出误差为高电平，并将锁存器的输出传送到下一级。

公开(公告)号：US20240055489A1

公开(公告)日：2024-02-15

申请号：US17994027

申请日：2022-11-25

Applicant: University of Electronic Science and Technology of China

Inventor： Bo ZHANG ,  Lingying WU ,  Yuting LIU ,  Wentong ZHANG ,  Zhaoji LI

IPC: H01L29/40 ,  H01L29/423

CPC classification number: H01L29/407 ,  H01L29/404 ,  H01L29/4238

Abstract: A homogenization field device with low specific on-resistance based on multidimensional coupled voltage dividing mechanism includes a first conductive type semiconductor substrate, a first conductive type well region, a first conductive type semiconductor contact region, a second conductive type drift region, a second conductive type well region, a second conductive type semiconductor contact region, a first dielectric oxide layer, a second dielectric oxide layer, a third dielectric oxide layer, a fourth dielectric oxide layer, a polycrystalline silicon electrode of a floating field plate, a polycrystalline silicon electrode of a control gate, a first layer of metal strips and a second layer of metal strips. The first dielectric oxide layer and the polycrystalline silicon electrode of the floating field plate form a vertical floating field plate, and the first layer of metal strips, the second layer of metal strips and the fourth dielectric oxide layer form a surface fixed dielectric capacitor.

公开(公告)号：US20220367712A1

公开(公告)日：2022-11-17

申请号：US17367442

申请日：2021-07-05

Applicant: University of Electronic Science and Technology of China

Inventor： Ming QIAO ,  Liu YUAN ,  Zhao WANG ,  Wenliang LIU ,  Bo ZHANG

IPC: H01L29/78 ,  H01L29/40 ,  H01L29/06 ,  H01L29/10

Abstract: A power semiconductor device includes a P-type substrate, an N-type well region, a P-type body region, a gate oxide layer, a polysilicon gate, a first oxide layer, a first N+ contact region, a first P+ contact region, drain metal, a first-type doped region, and a gate oxide layer. An end of the P-type body region is flush with or exceeds an end of the polysilicon gate, wherein Cgd of the power semiconductor device is reduced and a switching frequency of the power semiconductor device is increased. A polysilicon field plate connected with a source is introduced over a drift region that is not only shield an influence of the polysilicon gate on the drift region, thereby eliminating Cgd caused by overlapping of traditional polysilicon gate and drift region, but also enable the power semiconductor device to have strong robustness against an hot carrier effect.

公开(公告)号：US20220352304A1

公开(公告)日：2022-11-03

申请号：US17351267

申请日：2021-06-18

Applicant: University of Electronic Science and Technology of China

Inventor： Ming QIAO ,  Shuhao ZHANG ,  Zhangyi'an YUAN ,  Dican HOU ,  Bo ZHANG

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L29/08

Abstract: A lateral power semiconductor device includes a first type doping substrate at a bottom of the lateral power semiconductor device, a second type doping drift region, a second type heavy doping drain, a first type doping body; a first type heavy doping body contact and a second type heavy doping source, where dielectric layers are on a right side of the second type heavy doping source; the dielectric layers are arranged at intervals in a longitudinal direction in the first type doping body, and between adjacent dielectric layers in the longitudinal direction is the first type doping body; and a polysilicon is surrounded by the dielectric layer at least on a right side. Compared with conventional trench devices, the lateral power semiconductor device introduces a lateral channel, to increase a current density, thereby realizing a smaller channel on-resistance.

公开(公告)号：US20210336052A1

公开(公告)日：2021-10-28

申请号：US17005354

申请日：2020-08-28

Applicant: University of Electronic Science and Technology of China

Inventor： Ming QIAO ,  Zhengkang WANG ,  Shida DONG ,  Bo ZHANG

IPC: H01L29/78 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/423

Abstract: A power MOS device with low gate charge and a method for manufacturing the same. The device includes an M-shaped gate structure, which reduces the overlapped area between control gate electrode and split gate electrode. A low-k material is introduced to reduce dielectric constant of the isolation medium material. The combination of the M-shaped gate structure and low-k material can reduce parasitic capacitance Cgs of the device, thereby increasing switching speed and reducing switching losses.