公开(公告)号：US11424331B1

公开(公告)日：2022-08-23

申请号：US17348790

申请日：2021-06-16

Applicant: University of Electronic Science and Technology of China

Inventor： Ming Qiao ,  Dingxiang Ma ,  Zhengkang Wang ,  Bo Zhang

IPC: H01L29/40 ,  H01L29/78 ,  H01L29/66

Abstract: A power semiconductor device for improving a hot carrier injection is provided. A drain field plate is introduced at one side of a drain in a dielectric trench and connected to a drain electrode, having identical electric potential, thereby improving hole injection effects at a drain side of the dielectric trench. A shield gate field plate is introduced at one side of a source electrode in the dielectric trench and is connected to the source electrode or ground, thereby forming a shield gate. While decreasing gate drain parasitic capacitance Cgd, electron injection effects at a source electrode side of the dielectric trench are improved. With a trench etching method, the improvement of hot carrier injection can also be achieved by making carriers avoid a side wall of the dielectric trench on a path.

公开(公告)号：US11211486B2

公开(公告)日：2021-12-28

申请号：US17005354

申请日：2020-08-28

Applicant: University of Electronic Science and Technology of China

Inventor： Ming Qiao ,  Zhengkang Wang ,  Shida Dong ,  Bo Zhang

IPC: H01L29/78 ,  H01L21/82 ,  H01L29/423 ,  H01L29/66 ,  H01L21/8234

Abstract: A power MOS device with low gate charge and a method for manufacturing the same. The device includes an M-shaped gate structure, which reduces the overlapped area between control gate electrode and split gate electrode. A low-k material is introduced to reduce dielectric constant of the isolation medium material. The combination of the M-shaped gate structure and low-k material can reduce parasitic capacitance Cgs of the device, thereby increasing switching speed and reducing switching losses.

公开(公告)号：US10910362B2

公开(公告)日：2021-02-02

申请号：US16017978

申请日：2018-06-25

Applicant: University of Electronic Science and Technology of China

Inventor： Ming Qiao ,  Zhao Qi ,  Jiamu Xiao ,  Longfei Liang ,  Danye Liang ,  Bo Zhang

IPC: H01L27/02 ,  H01L29/10 ,  H01L29/78 ,  H01L29/08

Abstract: The present invention provides a high voltage ESD protection device including a P-type substrate; a first NWELL region located on the left of the upper part of the P-type substrate; an NP contact region located on the upper part of the first NWELL region; an N+ contact region located on the right of the upper part of the P-type substrate apart from the first NWELL region; a P+ contact region tangential to the right side of the N+ contact region; a NTOP layer arranged on the right of the NP contact region inside the first NWELL region. The NP contact region is connected to a metal piece to form a metal anode. The N+ contact region and the P+ contact region are connected by a metal piece to form a metal cathode.

公开(公告)号：US10672896B2

公开(公告)日：2020-06-02

申请号：US15695078

申请日：2017-09-05

Applicant: University of Electronic Science and Technology of China

Inventor： Wanjun Chen ,  Yijun Shi ,  Jie Liu ,  Xingtao Cui ,  Guanhao Hu ,  Chao Liu ,  Qi Zhou ,  Bo Zhang

IPC: H01L29/205 ,  H01L29/20 ,  H01L29/778 ,  H01L29/66 ,  H01L29/423 ,  H01L29/417 ,  H01L29/51 ,  H01L29/739

Abstract: The present invention relates to the field of semiconductor switches, and relates more particularly to a GaN-based bidirectional switch device. The present invention provides a gate-controlled tunneling bidirectional switch device without Ohmic-contact, which avoids a series of negative effects (such as current collapse, incompatibility with traditional CMOS process) caused by the high temperature ohm annealing process. Each insulated gate structure near schottky-contact controls the band structure of the schottky-contact to change the working state of the device, realizing the bidirectional switch's ability of bidirectional conducting and blocking. Due to the only presence of schottky in this invention, no heavy elements such as gold is needed, and this device is compatible with traditional CMOS technology.

公开(公告)号：US10374506B1

公开(公告)日：2019-08-06

申请号：US16174307

申请日：2018-10-30

Applicant: University of Electronic Science and Technology of China

Inventor： Ze-kun Zhou ,  Jun-Lin Qian ,  Xiao-Lin Liu ,  Yue Shi ,  Zhuo Wang ,  Bo Zhang

IPC: H02M1/08 ,  H02M3/156 ,  H03K21/08 ,  H02M1/00

Abstract: An adaptive control method for zero voltage switching belongs to the field of integrated circuit. In the present invention, the difference between the turn-on time of the power tube and the time of the lowest drain voltage of the power tube in the switching cycle is quantified by the reversible counter, and the quantized result is transmitted to the next switching cycle to adjust the turn-on time of the power tube through the final count result of the reversible counter, so that the power tube after being adjusted can be turned on when the drain voltage of the power tube is the lowest, thus reducing the switching loss. The present invention can adaptively turn on the power tube when the drain voltage of the power tube reaches minimum, thus, realizing the zero-voltage switching, reducing the switching loss of the switching power supply, widening the application range.

公开(公告)号：US10340373B2

公开(公告)日：2019-07-02

申请号：US15600795

申请日：2017-05-22

Applicant: University of Electronic Science and Technology of China

Inventor： Xiaorong Luo ,  Gaoqiang Deng ,  Kun Zhou ,  Qing Liu ,  Linhua Huang ,  Tao Sun ,  Bo Zhang

IPC: H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/74 ,  H01L29/739 ,  H01L29/861

Abstract: The present invention relates to the technical field of the power semiconductor device relates to a reverse conducting insulated gate bipolar transistor (RC-IGBT). The RC-IGBT comprises a P-type region, an N-type emitter region, a P-type body contact region, a dielectric trench, a collector region, and an electrical filed cutting-off region. The beneficial effect of the present invention is that, when compared with traditional RC-IGBT, the IGBT of the present invention can eliminate negative resistance effect and effectively improve the performance of forward and reverse conduction.

公开(公告)号：US10304931B2

公开(公告)日：2019-05-28

申请号：US15623371

申请日：2017-06-14

Applicant: University of Electronic Science and Technology of China

Inventor： Xiaorong Luo ,  Fu Peng ,  Chao Yang ,  Jie Wei ,  Siyu Deng ,  Dongfa Ouyang ,  Bo Zhang

IPC: H01L29/06 ,  H01L29/15 ,  H01L29/207 ,  H01L29/423 ,  H01L29/78 ,  H01L29/10 ,  H01L29/20 ,  H01L29/778

Abstract: The present invention belongs to the field of semiconductor technology and relates to a polarization-doped enhancement mode HEMT device. The technical solution of the present invention grows the first barrier layer and the second barrier layer that contain gradient Al composition sequentially on the buffer layer. The gradient trends of the two layers are opposite. The three-dimensional electron gas (3DEG) and the three-dimensional hole gas (3DHG) are induced and generated in the barrier layers due to the inner polarization difference respectively. A trench insulated gate structure is at one side of the source which is away from the metal drain and is in contact with the source. First, since the highly concentrated electrons exist in the entire first barrier layer, the on-state current is improved greatly. Second, the vertical conductive channel between the source and the 3DEG are pinched off by the 3DHG, so as to realize the enhancement mode.

公开(公告)号：US10042379B1

公开(公告)日：2018-08-07

申请号：US15867717

申请日：2018-01-11

Applicant: University of Electronic Science and Technology of China

Inventor： Zekun Zhou ,  Xiang Li ,  Yandong Yuan ,  Yue Shi ,  Zhuo Wang ,  Bo Zhang

IPC: H03K3/42 ,  G05F3/26

Abstract: A sub-threshold low-power and resistor-less reference circuit which is related to the field of reference circuit technology of analog circuit includes a negative-temperature-coefficient voltage generating circuit, a positive-temperature-coefficient voltage generating circuit and a current balancing circuit. The negative-temperature-coefficient voltage generating circuit generates a negative-temperature-coefficient voltage VCTAT based on the negative-temperature voltage characteristic of base-emitter PN junction of the bipolar tsansistor. On the other hand, the positive-temperature-coefficient voltage generating circuit generates a positive-temperature-coefficient voltage VPTAT based on the positive-temperature voltage characteristic of the NMOS transistor operating in a sub-threshold region. The current balancing circuit is configured to eliminate the error current caused due to the difference of the current mirror when the two voltages with different temperature characteristics are superposed to output a reference voltage.

公开(公告)号：US12212357B2

公开(公告)日：2025-01-28

申请号：US17873134

申请日：2022-07-25

Applicant: University of Electronic Science and Technology of China

Inventor： Bo Zhang ,  Zhongqian Niu ,  Xiaobo Yang ,  Bingli Dai ,  Yi Hu ,  Jicong Zhang ,  Yong Fan ,  Ke Liu ,  Zhi Chen

IPC: H04B1/40 ,  H03D7/16

Abstract: The present disclosure provides a GaAs monolithic integrated terahertz low-noise communication system transceiver front-end, including an intermediate frequency circuit and a terahertz circuit. The terahertz circuit includes a local oscillator frequency tripler, a local oscillator unidirectional 3 dB filter coupler, a radio frequency 180° filter coupler, and two terahertz GaAs monolithic integrated subharmonic mixers. The local oscillator unidirectional 3 dB filter coupler and the radio frequency 180° filter coupler each include one ring-cylindrical resonant cavity and four rectangular waveguides. The ring-cylindrical resonant cavity is divided into four rectangular waveguides which are correspondingly connected to the four sector-annular resonant cavities, respectively. The present disclosure suppresses the local oscillator noise by adopting a local oscillator unidirectional 3 dB filter coupler and a radio frequency 180° filter coupler with both coupling and filtering functions, thereby achieving a low local oscillator noise transceiver front-end.

公开(公告)号：US11855203B2

公开(公告)日：2023-12-26

申请号：US17367442

申请日：2021-07-05

Applicant: University of Electronic Science and Technology of China

Inventor： Ming Qiao ,  Liu Yuan ,  Zhao Wang ,  Wenliang Liu ,  Bo Zhang

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/40

CPC classification number: H01L29/7824 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/402

Abstract: A power semiconductor device includes a P-type substrate, an N-type well region, a P-type body region, a gate oxide layer, a polysilicon gate, a first oxide layer, a first N+ contact region, a first P+ contact region, drain metal, a first-type doped region, and a gate oxide layer. An end of the P-type body region is flush with or exceeds an end of the polysilicon gate, wherein Cgd of the power semiconductor device is reduced and a switching frequency of the power semiconductor device is increased. A polysilicon field plate connected with a source is introduced over a drift region that is not only shield an influence of the polysilicon gate on the drift region, thereby eliminating Cgd caused by overlapping of traditional polysilicon gate and drift region, but also enable the power semiconductor device to have strong robustness against an hot carrier effect.