公开(公告)号：US11710681B2

公开(公告)日：2023-07-25

申请号：US17495788

申请日：2021-10-06

Applicant: UTAC Headquarters Pte. Ltd.

Inventor： Tanawan Chaowasakoo ,  Hua Hong Tan ,  Alexander Lucero Laylo ,  Thanawat Jaengkrajarng

IPC: H01L23/495 ,  H01L23/31 ,  H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  H01L25/07 ,  H01L21/56

CPC classification number: H01L23/49513 ,  H01L23/3128 ,  H01L23/49517 ,  H01L23/49541 ,  H01L23/49575 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/40 ,  H01L24/49 ,  H01L24/83 ,  H01L24/84 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/074 ,  H01L25/50 ,  H01L21/56 ,  H01L23/3107 ,  H01L2224/32245 ,  H01L2224/8384 ,  H01L2224/83815 ,  H01L2224/8484 ,  H01L2224/84815 ,  H01L2924/181

Abstract: An embodiment related to a device. The device includes a first die with first and second die surfaces. The second die surface is bonded to a first die attach pad (DAP) disposed on a first substrate surface of a package substrate and the first die surface includes a first die contact pad. The device also includes a first clip bond including a first clip bond horizontal planar portion attached to the first die contact pad on the first die surface, and a first clip bond vertical portion disposed on an edge of the first clip bond horizontal planar portion. The first clip bond vertical portion is attached to a first substrate bond pad on the first substrate surface. The device further includes a first conductive clip-die bonding layer with spacers on the first die contact pad of the first die. The first conductive clip-die bonding layer bonds the first clip bond horizontal planar portion to the first die contact pad, and the spacers maintain a uniform Bond Line Thickness (BLT) of the first conductive clip-die bonding layer.

公开(公告)号：US11177301B2

公开(公告)日：2021-11-16

申请号：US16687659

申请日：2019-11-18

Applicant: UTAC Headquarters Pte. Ltd.

Inventor： Hua Hong Tan ,  Chee Kay Chow ,  Thian Hwee Tan ,  Wedanni Linsangan Micla ,  Enrique Jr Sarile ,  Mario Arwin Fabian ,  Dennis Tresnado ,  Antonino Ii Milanes ,  Ming Koon Ang ,  Kian Soo Lim ,  Mauro Jr. Dionisio ,  Teddy Joaquin Carreon

IPC: H01L27/14 ,  H01L27/146

Abstract: A method for forming a semiconductor package is disclosed. The method includes providing a package substrate having top and bottom major package substrate surfaces, the top major package surface including a die attach region. A die having first and second major die surfaces is attached onto the die attach region. The second major die surface is attached to the die attach region. The first major die surface includes an die active region and a cover adhesive region surrounding the die active region. The method also includes applying a cover adhesive to the cover adhesive region on the first major die surface. A protective cover with first and second major cover surfaces and side surfaces is attached to the die using the cover adhesive. The second major cover surface contacts the cover adhesive. The protective cover covers the die active region. The protective cover includes a discontinuity on at least one of the side surfaces. An encapsulant is disposed on the package substrate to cover exposed portions of the package substrate, die and bond wires and side surfaces of the protective cover, while leaving the first major cover surface exposed. The discontinuity enhances adhesion of the encapsulant to the protective cover.

公开(公告)号：US11139233B2

公开(公告)日：2021-10-05

申请号：US16886728

申请日：2020-05-28

Applicant: UTAC Headquarters Pte. Ltd.

Inventor： Hua Hong Tan ,  Wilson Poh Leng Ong ,  Kriangsak Sae Le ,  Saravuth Sirinorakul ,  Somsak Phukronghin ,  Paweena Phatto

IPC: H01L23/498 ,  H01L23/16 ,  H01L21/48 ,  H01L23/31 ,  H01L21/52 ,  H01L21/56 ,  H01L23/055 ,  H01L23/04 ,  H01L23/24 ,  H01L23/00

Abstract: A method for forming a semiconductor package is disclosed herein. The method includes forming a package substrate having a first major surface and a second major surface opposite to the first major surface. The package substrate includes a recess region below the first major surface defined with a die region and a non-die region surrounding the die region. A semiconductor die is disposed in the die region within the recess region. A dam structure is disposed within the recess region. The dam structure surrounds the semiconductor die and extends upwardly to a height below the first major surface of the package substrate. The method also includes dispensing a liquid encapsulant material into the recess region. The liquid encapsulant material is surrounded by the dam structure and extends upwardly to a height below the height of the dam structure. A package lid is attached to the package substrate.

公开(公告)号：US09508623B2

公开(公告)日：2016-11-29

申请号：US14731484

申请日：2015-06-05

Applicant: UTAC Headquarters Pte. Ltd.

Inventor： Nathapong Suthiwongsunthorn ,  Antonio Jr. Bambalan Dimaano ,  Rui Huang ,  Hua Hong Tan ,  Kriangsak Sae Le ,  Beng Yeung Ho ,  Nelson Agbisit De Vera ,  Roel Adeva Robles ,  Wedanni Linsangan Micla

IPC: H01L21/44 ,  H01L23/31 ,  H01L21/56 ,  H01L21/78 ,  H01L21/3105 ,  H01L21/683 ,  H01L23/00 ,  H01L23/544

CPC classification number: H01L23/3135 ,  H01L21/3105 ,  H01L21/561 ,  H01L21/566 ,  H01L21/568 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/544 ,  H01L24/11 ,  H01L24/13 ,  H01L24/94 ,  H01L2221/68327 ,  H01L2221/68336 ,  H01L2221/6834 ,  H01L2223/54426 ,  H01L2224/0391 ,  H01L2224/1134 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/94 ,  H01L2924/10156 ,  H01L2924/1815 ,  H01L2224/11 ,  H01L2924/014 ,  H01L2924/00014

Abstract: Semiconductor packages and methods for forming a semiconductor package are disclosed. The method includes providing a wafer having first and second major surfaces. The wafer is prepared with a plurality of dies and a plurality of external electrical contacts disposed on the first major surface of the wafer. The method includes processing the wafer. Processing the wafer includes separating the wafer into a plurality of individual dies. An individual die includes first and second major surfaces and first and second sidewalls, and the external electrical contacts are formed on the first major surface of the die. An encapsulant material is formed. The encapsulant material covers at least a portion of the first and second sidewalls of the die.

Abstract translation: 公开了用于形成半导体封装的半导体封装和方法。 该方法包括提供具有第一和第二主表面的晶片。 晶片由多个管芯和设置在晶片的第一主表面上的多个外部电触点制成。 该方法包括处理晶片。 处理晶片包括将晶片分离成多个单独的芯片。 单个管芯包括第一和第二主表面以及第一和第二侧壁，并且外部电触头形成在管芯的第一主表面上。 形成密封剂材料。 密封剂材料覆盖模具的第一和第二侧壁的至少一部分。