ASYNCHRONOUS ANALOG-TO-DIGITAL CONVERTER HAVING RATE CONTROL
    11.
    发明申请
    ASYNCHRONOUS ANALOG-TO-DIGITAL CONVERTER HAVING RATE CONTROL 有权
    具有速率控制的异步模数转换器

    公开(公告)号:US20140062751A1

    公开(公告)日:2014-03-06

    申请号:US13599539

    申请日:2012-08-30

    Abstract: An apparatus is provided. A comparison circuit is configured to receive an analog signal. A reference circuit is coupled to the comparison circuit and is configured to provide a plurality of reference signals to the comparison circuit. A conversion circuit is coupled to the comparison circuit and is configured to detect a change in the output of the comparison circuit. A time-to-digital converter (TDC) is coupled to the comparison circuit. A timer is coupled to the comparison circuit. A rate control circuit is coupled to the conversion circuit. An output circuit is coupled to the rate control circuit and the TDC, where the output circuit is configured to output at least one of a synchronous digital representation of the analog signal and an asynchronous digital representation of the analog signal.

    Abstract translation: 提供了一种装置。 比较电路被配置为接收模拟信号。 参考电路耦合到比较电路,并被配置为向比较电路提供多个参考信号。 A转换电路耦合到比较电路,并被配置为检测比较电路的输出的变化。 时间数字转换器(TDC)耦合到比较电路。 定时器耦合到比较电路。 速率控制电路耦合到转换电路。 输出电路耦合到速率控制电路和TDC,其中输出电路被配置为输出模拟信号的同步数字表示和模拟信号的异步数字表示中的至少一个。

    Enhanced Sub-Frame-Based-Framing for Wireless Communications
    12.
    发明申请
    Enhanced Sub-Frame-Based-Framing for Wireless Communications 审中-公开
    用于无线通信的增强的基于子帧的帧

    公开(公告)号:US20090175234A1

    公开(公告)日:2009-07-09

    申请号:US12350523

    申请日:2009-01-08

    CPC classification number: H04L27/2602 H04B7/2656 H04L5/005 H04L27/2613

    Abstract: A method of performing wireless communications. The method comprises, at a transmitting station, encoding a plurality of symbols into a frame. The method further comprises, from the transmitting station, transmitting the frame via a wireless communication to a receiving station. The frame comprises a plurality of sub-frames, wherein a first sub-frame in the plurality of sub-frames consists of a first number of symbols and a second sub-frame in the plurality of sub-frames consists of a second number of symbols. Finally, the first number differs from the second number.

    Abstract translation: 一种执行无线通信的方法。 该方法包括在发送站将多个符号编码成帧。 该方法还包括从发送站经由无线通信将帧发送到接收站。 所述帧包括多个子帧,其中所述多个子帧中的第一子帧由所述多个子帧中的第一数量的符号和第二子帧组成,所述第二子帧由第二数量的符号 。 最后,第一个数字与第二个数字不同。

    Computationally and memory efficient tone ordering scheme
    13.
    发明授权
    Computationally and memory efficient tone ordering scheme 有权
    计算和记忆效率音调排序方案

    公开(公告)号:US07496134B2

    公开(公告)日:2009-02-24

    申请号:US11043218

    申请日:2005-01-26

    CPC classification number: H04L27/2608 H04B1/38

    Abstract: An integrated circuit 18 is provided that includes a memory 32 and a memory modification component 33. The memory 32 maintains a bits count, a gain, and a tone order for each of a plurality of discrete multi-tone sub-channels. The memory modification component 33 operable to control an in-service modification of at least some of the bits count, the gain, and the tone order using a single bits, gains and tone order table.

    Abstract translation: 提供了包括存储器32和存储器修改组件33的集成电路18.存储器32维持多个离散多音调子频道中的每一个的比特计数,增益和音调顺序。 存储器修改组件33可用于使用单个位,增益和音调顺序表来控制比特计数,增益和音调顺序中的至少一些的在职修改。

    System for Ultrasound Color Doppler Imaging
    14.
    发明申请
    System for Ultrasound Color Doppler Imaging 审中-公开
    超声彩色多普勒成像系统

    公开(公告)号:US20120184856A1

    公开(公告)日:2012-07-19

    申请号:US13432880

    申请日:2012-03-28

    Abstract: Systems for color Doppler imaging in an ultrasound imaging system are disclosed herein. An ultrasound imaging system includes color Doppler imaging circuitry. The color Doppler imaging circuitry is configured to estimate flow parameters. The imaging circuitry includes a radio frequency (“RF”) demodulator configured to produce in-phase and quadrature components of an ultra-sound data vector. The RF demodulator includes a table in memory that stores interleaved sine and cosine values. The RF demodulator maintains an index value for the table having higher precision than is used to index the table. The RF demodulator rounds the index value for each access of the table. Each table access retrieves a sine value and a cosine value.

    Abstract translation: 本文公开了超声成像系统中的彩色多普勒成像系统。 超声成像系统包括彩色多普勒成像电路。 彩色多普勒成像电路被配置为估计流量参数。 成像电路包括被配置为产生超声数据向量的同相和正交分量的射频(“RF”)解调器。 RF解调器包括存储交错的正弦和余弦值的存储器中的表。 RF解调器为表具有比用于索引表的精度更高的索引值。 RF解调器舍入表的每个访问的索引值。 每个表访问检索正弦值和余弦值。

    Patent Fluoroscopy System with Spatio-Temporal Filtering
    15.
    发明申请
    Patent Fluoroscopy System with Spatio-Temporal Filtering 有权
    专利荧光透视系统与时空滤波

    公开(公告)号:US20120183196A1

    公开(公告)日:2012-07-19

    申请号:US13352865

    申请日:2012-01-18

    Abstract: A system for processing real-time fluoroscopy image sequences. A first image frame is loaded into an upper level memory of a hierarchical memory system that is coupled to at least one processing core. The first image frame is processed with an object detection filter to form a likelihood image frame. The first image frame and the likelihood image frame is spatially filtered using a spatial filter look up table (LUT) stored in an L1 level memory of the processing core. The likelihood image frame is temporally filtering using a temporal filter LUT stored in the L1 level memory.

    Abstract translation: 一种用于处理实时荧光透视图像序列的系统。 第一图像帧被加载到耦合到至少一个处理核的分层存储器系统的上层存储器中。 用对象检测滤波器处理第一图像帧以形成似然图像帧。 使用存储在处理核心的L1级存储器中的空间滤波器查找表(LUT)对第一图像帧和似然图像帧进行空间滤波。 使用存储在L1级存储器中的时间滤波器LUT对似然图像帧进行时间滤波。

    Digital timing recovery method for communication receivers
    16.
    发明授权
    Digital timing recovery method for communication receivers 有权
    通信接收机的数字定时恢复方法

    公开(公告)号:US06983032B2

    公开(公告)日:2006-01-03

    申请号:US09941002

    申请日:2001-08-28

    CPC classification number: H04L7/0337 H04L27/2657

    Abstract: The present invention provides an apparatus, system and method for synchronizing a local clock signal with a remote clock signal in a communication network. Phase information is used to calculate a number of “clock jitters” per unit of time needed to synchronize the locally generated clock with the remote clock. Introducing (removing) a given amount of delay at a particular point in the local clock signal results in a positive (negative) jitter in which its minimum value defines the jitter resolution. The jitters are introduced to the local clock signal from a plurality of tapped delay line elements (310) selected by a phase selector (350) in response to a timing correction signal issued by a phase error module (520).

    Abstract translation: 本发明提供了一种在本地时钟信号与通信网络中的远程时钟信号同步的装置,系统和方法。 相位信息用于计算在本地生成的时钟与远程时钟同步所需的每单位时间的“时钟抖动”数量。 在本地时钟信号的特定点引入(去除)给定量的延迟会导致正(负)抖动,其中最小值定义抖动分辨率。 响应于由相位误差模块(520)发出的定时校正信号,从由相位选择器(350)选择的多个抽头延迟线元件(310)中将抖动引入本地时钟信号。

    Automatic gain control for a multi-stage gain system
    17.
    发明申请
    Automatic gain control for a multi-stage gain system 有权
    多级增益系统的自动增益控制

    公开(公告)号:US20050127993A1

    公开(公告)日:2005-06-16

    申请号:US10966981

    申请日:2004-10-15

    CPC classification number: H03G3/001 H03G1/0088 H03G3/3036

    Abstract: Systems and methods are disclosed for providing automatic gain control of a multi-stage system. A method can include defining at least one parameter that is adapted to at least one of maximize hardware capacity of each of a plurality of gain stages and mitigate part-to-part variations of the multi-stage system. An order is selected for training the plurality of stages based on relative noise dominance for the plurality of stage. For a given stage of the plurality of stages, which is selected according to the selected order, output signals of the multi-stage system are measured over a plurality of gain settings for the given stage. A gain setting of the given stage of the multi-stage system also is configured based on the measured output signals relative to the at least one parameter defined for the given stage. The plurality of gain stages can include an analog equalizer as well programmable gain amplifiers connected in series.

    Abstract translation: 公开了用于提供多级系统的自动增益控制的系统和方法。 一种方法可以包括定义至少一个适于至少一个参数的参数,其中最小化多个增益级中的每一个的硬件容量并减轻多级系统的部分变化。 选择用于基于多个级的相对噪声优势来训练多个级的顺序。 对于根据所选择的顺序选择的多个级的给定级,在给定级的多个增益设置上测量多级系统的输出信号。 基于相对于为给定阶段定义的至少一个参数的测量输出信号,配置多级系统的给定级的增益设置。 多个增益级可以包括串联连接的模拟均衡器以及可编程增益放大器。

    Asynchronous analog-to-digital converter
    18.
    发明授权
    Asynchronous analog-to-digital converter 有权
    异步模数转换器

    公开(公告)号:US08760329B2

    公开(公告)日:2014-06-24

    申请号:US13599452

    申请日:2012-08-30

    Abstract: A method is provided. An analog signal is received. The analog input signal is compared to first and second reference signals to generate a first comparison result, and the first comparison result and a first time stamp corresponding to the first comparison result are registered. A first portion of a digital signal is generated from the first comparison result. If the comparison result remains substantially the same for a predetermined interval, an ADC is enabled to generate a second comparison result at a sampling instant. A second time stamp that corresponds to the sampling instant is generated. The second comparison result and a second time stamp corresponding to the first comparison result are registered, and a second portion of the digital signal is generated from the second comparison result.

    Abstract translation: 提供了一种方法。 接收模拟信号。 将模拟输入信号与第一和第二参考信号进行比较以产生第一比较结果,并且登记与第一比较结果对应的第一比较结果和第一时间戳。 从第一比较结果生成数字信号的第一部分。 如果比较结果在预定间隔内保持基本相同,则ADC能够在采样时刻产生第二比较结果。 产生对应于采样时刻的第二时间戳。 登记与第一比较结果相对应的第二比较结果和第二时间戳,并且从第二比较结果生成数字信号的第二部分。

    ASYNCHRONOUS ANALOG-TO-DIGITAL CONVERTER HAVING ADAPATIVE REFERENCE CONTROL
    19.
    发明申请
    ASYNCHRONOUS ANALOG-TO-DIGITAL CONVERTER HAVING ADAPATIVE REFERENCE CONTROL 有权
    具有适应参考控制的异步模数转换器

    公开(公告)号:US20140062735A1

    公开(公告)日:2014-03-06

    申请号:US13599491

    申请日:2012-08-30

    CPC classification number: H03M1/12 H03M1/125 H03M1/127 H03M1/182

    Abstract: A method is provided. An analog signal is received. The analog input signal is compared to first and second reference signals to generate a first comparison result, and the first comparison result and a first time stamp corresponding to the first comparison result are registered. A first portion of a digital signal is generated from the first comparison result. At least one of the first and second reference signals is adjusted. A second comparison result is generated if the analog signal reaches an adjusted one of the first and second reference signals within a predetermined interval, and a second portion of the digital signal is generated from the second comparison result.

    Abstract translation: 提供了一种方法。 接收模拟信号。 将模拟输入信号与第一和第二参考信号进行比较以产生第一比较结果,并且登记与第一比较结果对应的第一比较结果和第一时间戳。 从第一比较结果生成数字信号的第一部分。 调整第一和第二参考信号中的至少一个。 如果模拟信号在预定间隔内达到第一和第二参考信号中调整的一个,并且从第二比较结果产生数字信号的第二部分,则产生第二比较结果。

    Receiver-side selection of DSL communications mode
    20.
    发明授权
    Receiver-side selection of DSL communications mode 有权
    DSL通信模式的接收方选择

    公开(公告)号:US07555049B2

    公开(公告)日:2009-06-30

    申请号:US11220089

    申请日:2005-09-06

    CPC classification number: H04M11/062

    Abstract: A client premises digital subscriber line (DSL) modem having multi-mode capability is disclosed. In initialization, the modem estimates whether channel conditions are such that digital processing of the received data according to a lower data rate DSL standard, such as ADSL2, may result in a higher effective data rate than receipt and processing according to a higher data rate DSL standard, such as ADSL2+. If so, the DSL modem configures itself, such as by configuring its filter characteristics and sampling frequency, to receive and process data according to the lower data rate DSL standard; the transmitting modem, for example at a central office or service area interface, may continue to operate according to the higher data rate standard (with its bit loading corresponding to a subset of subchannels). The receiving DSL modem processes the payload data according to the lower standard, while processing control messages according to the higher standard.

    Abstract translation: 公开了具有多模式能力的客户端数字用户线(DSL)调制解调器。 在初始化中,调制解调器估计信道条件是否使得根据诸如ADSL2的较低数据速率DSL标准的接收数据的数字处理可以导致比根据较高数据速率DSL的接收和处理更高的有效数据速率 标准,如ADSL2 +。 如果是这样,则DSL调制解调器通过配置其滤波器特性和采样频率来配置自身,以根据较低数据速率DSL标准接收和处理数据; 发射调制解调器例如在中心局或服务区接口处可以根据较高的数据速率标准(其位加载对应于子信道子集)继续运行。 接收DSL调制解调器根据较低的标准处理有效载荷数据,同时根据较高的标准处理控制消息。

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