公开(公告)号：US20240032441A1

公开(公告)日：2024-01-25

申请号：US17892162

申请日：2022-08-22

Applicant: United Microelectronics Corp.

Inventor： Chih-Wei Kuo ,  Hung-Chan Lin ,  Chung Yi Chiu

IPC: H01L43/04 ,  H01L27/22 ,  H01L43/06 ,  H01L43/10 ,  H01L43/14

CPC classification number: H01L43/04 ,  H01L27/222 ,  H01L43/06 ,  H01L43/10 ,  H01L43/14

Abstract: Provided is a magnetoresistive random access memory (MRAM) device including a bottom electrode, a magnetic tunnel junction (MTJ) structure, a first spin orbit torque (SOT) layer, a cap layer, a second SOT layer, an etch stop layer, and an upper metal line layer. The MTJ structure is disposed on the bottom electrode. The first SOT layer is disposed on the MTJ structure. The cap layer is disposed on the first SOT layer. The second SOT layer is disposed on the cap layer. The etch stop layer is disposed on the second SOT layer. The upper metal line layer penetrates though the etch stop layer and is landed on the second SOT layer.

公开(公告)号：US20230263072A1

公开(公告)日：2023-08-17

申请号：US18138137

申请日：2023-04-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Wei Kuo

IPC: H10N50/80 ,  H10B61/00 ,  H10N50/01

CPC classification number: H10N50/80 ,  H10B61/00 ,  H10N50/01

Abstract: A method of manufacturing a magnetic tunnel junction (MTJ) device, including steps of forming a dielectric layer comprising a metal line therein on a substrate, forming a magnetic tunneling junction element over the metal line, depositing a silicon nitride cap layer conformally covering the magnetic tunneling junction element and the dielectric layer, depositing a tantalum containing cap layer conformally covering the silicon nitride cap layer, removing parts of the tantalum containing cap layer and the silicon nitride cap layer, and disposing a metal plug directly on the magnetic tunneling junction element.

公开(公告)号：US11271154B2

公开(公告)日：2022-03-08

申请号：US16529740

申请日：2019-08-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Wei Kuo ,  Ting-Hsiang Huang ,  Yu-Tsung Lai ,  Jiunn-Hsiung Liao

IPC: H01L45/00 ,  H01L43/02 ,  H01L41/297

Abstract: A magnetic tunnel junction (MTJ) device includes two magnetic tunnel junction elements and a metal interconnection. The two magnetic tunnel junction elements are arranged side by side at a first direction. The metal interconnection is disposed between the magnetic tunnel junction elements, wherein the metal interconnection includes a contact plug part having a long shape at a top view, and the long shape has a length at a second direction larger than a width at the first direction, wherein the second direction is orthogonal to the first direction.

公开(公告)号：US20210296576A1

公开(公告)日：2021-09-23

申请号：US17336295

申请日：2021-06-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Wei Kuo ,  Tai-Cheng Hou ,  Yu-Tsung Lai ,  Jiunn-Hsiung Liao

IPC: H01L43/12 ,  H01L43/02

Abstract: A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate; forming a first top electrode on the first MTJ and a second top electrode on the second MTJ; forming a passivation layer on the first MTJ and the second MTJ; removing part of the passivation layer so that a top surface of all of the remaining passivation layer is lower than a top surface of the first electrode; and forming a ultra low-k (ULK) dielectric layer on the first MTJ and the second MTJ.

公开(公告)号：US20200373479A1

公开(公告)日：2020-11-26

申请号：US16439712

申请日：2019-06-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Wei Kuo ,  Meng-Jun Wang ,  Yi-Wei Tseng ,  Yu-Tsung Lai ,  Jiunn-Hsiung Liao

IPC: H01L43/02 ,  H01L43/12

Abstract: A semiconductor device includes: a magnetic tunneling junction (MTJ) on a substrate; a first inter-metal dielectric (IMD) layer around the MTJ; a metal interconnection on and directly contacting the MTJ; a second IMD layer on the first IMD layer and around the metal interconnection; and a metal oxide layer on the second IMD layer and around the metal interconnection.

公开(公告)号：US10804138B2

公开(公告)日：2020-10-13

申请号：US15712153

申请日：2017-09-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Wei Kuo ,  Yu-Tsung Lai ,  Jiunn-Hsiung Liao

IPC: H01L21/768

Abstract: A method for fabricating a semiconductor device includes the steps of: providing a first dielectric layer having a metal layer therein; forming a second dielectric layer on the first dielectric layer and the metal layer; forming a metal oxide layer on the second dielectric layer; performing a first etching process by using a chlorine-based etchant to remove part of the metal oxide layer to forma via opening and expose the second dielectric layer; forming a block layer on sidewalls of the metal oxide layer and a top surface of the second dielectric layer; and performing a second etching process by using a fluorine-based etchant to remove part of the block layer and part of the second dielectric layer for exposing a top surface of the metal layer.

公开(公告)号：US09741614B1

公开(公告)日：2017-08-22

申请号：US15206330

申请日：2016-07-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Wei Kuo ,  Yu-Tsung Lai ,  Jiunn-Hsiung Liao

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/02 ,  H01L21/033 ,  H01L21/027

CPC classification number: H01L21/0273 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76811 ,  H01L21/76816

Abstract: A method of forming trenches and a via by self-aligned double patterning includes providing a dielectric layer covered by an SiOC layer, a TiN layer and a SiON layer from top to bottom. At least two mandrels are formed on the SiOC layer. Later, two spacers are formed respectively at two sidewalls of each mandrel. Subsequently, the mandrels are removed. The SiOC layer and the TiN layer are patterned by using the spacers to form numerous recesses. The spacers are then removed. A mask layer with a via pattern is formed to cover the SiOC layer. A via is formed in the dielectric layer by taking the mask layer as a mask. After that, the mask layer is removed. Finally, numerous trenches are formed in the dielectric layer by taking the SiOC layer and the TiN layer as a mask.

公开(公告)号：US12245521B2

公开(公告)日：2025-03-04

申请号：US17885521

申请日：2022-08-10

Applicant: United Microelectronics Corp.

Inventor： Chih-Wei Kuo ,  Chung Yi Chiu ,  Yi-Wei Tseng ,  Hsuan-Hsu Chen ,  Chun-Lung Chen

IPC: H10N52/80 ,  H10B61/00 ,  H10N52/00 ,  H10N52/01

Abstract: A magnetic memory including a substrate, a spin-orbit torque (SOT) layer, a magnetic tunnel junction (MTJ) stack, a first protection layer, and a second protection layer is provided. The SOT layer is located over the substrate. The MTJ stack is located on the SOT layer. The first protection layer and the second protection layer are located on the sidewall of the MTJ stack. The first protection layer is located between the second protection layer and the MTJ stack. There is a notch between the second protection layer and the SOT layer.

公开(公告)号：US20240016067A1

公开(公告)日：2024-01-11

申请号：US17885521

申请日：2022-08-10

Applicant: United Microelectronics Corp.

Inventor： Chih-Wei Kuo ,  Chung Yi Chiu ,  Yi-Wei Tseng ,  Hsuan-Hsu Chen ,  Chun-Lung Chen

IPC: H01L43/04 ,  H01L27/22 ,  H01L43/06 ,  H01L43/14

CPC classification number: H01L43/04 ,  H01L27/222 ,  H01L43/06 ,  H01L43/14

Abstract: A magnetic memory including a substrate, a spin-orbit torque (SOT) layer, a magnetic tunnel junction (MTJ) stack, a first protection layer, and a second protection layer is provided. The SOT layer is located over the substrate. The MTJ stack is located on the SOT layer. The first protection layer and the second protection layer are located on the sidewall of the MTJ stack. The first protection layer is located between the second protection layer and the MTJ stack. There is a notch between the second protection layer and the SOT layer.

公开(公告)号：US20230413579A1

公开(公告)日：2023-12-21

申请号：US18242014

申请日：2023-09-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Wei Kuo ,  Tai-Cheng Hou ,  Yu-Tsung Lai ,  Jiunn-Hsiung Liao

IPC: H10B61/00 ,  H10N50/01 ,  H10N50/10 ,  H10N50/80

CPC classification number: H10B61/22 ,  H10N50/01 ,  H10N50/10 ,  H10N50/80

Abstract: A semiconductor device includes a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate, a first top electrode on the first MTJ and a second top electrode on the second MTJ, a first spacer and a second spacer around the first MTJ, a third spacer and a fourth spacer around the second MTJ, a passivation layer between the second spacer and the third spacer as a top surface of the passivation layer includes a V-shape, and an ultra low-k (ULK) dielectric layer on the passivation layer and around the first MTJ and the second MTJ.