公开(公告)号：US20170117372A1

公开(公告)日：2017-04-27

申请号：US14923409

申请日：2015-10-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： DONGDONG LI ,  Ko-Chi Chen ,  Shen-De Wang

IPC: H01L29/423 ,  H01L29/788 ,  H01L29/66 ,  H01L27/115

CPC classification number: H01L29/42328 ,  H01L27/11534 ,  H01L29/42336 ,  H01L29/66825

Abstract: The present invention provides a semiconductor device, including a substrate with a memory region and a logic region, the substrate having a recess disposed in the memory region, a logic gate stack disposed in the logic region, and a non-volatile memory disposed in the recess. The non-volatile memory includes at least two floating gates and at least two control gates disposed on the floating gates, where each floating gate has a step-shaped bottom, and the step-shaped bottom includes a first bottom surface and a second bottom surface lower than the first bottom surface.

公开(公告)号：US20170110469A1

公开(公告)日：2017-04-20

申请号：US14950424

申请日：2015-11-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Liang Yi ,  Ko-Chi Chen ,  Shen-De Wang

IPC: H01L27/115 ,  H01L29/423

CPC classification number: H01L27/11578 ,  H01L21/28273 ,  H01L27/11524 ,  H01L27/11529 ,  H01L29/42328 ,  H01L29/42336 ,  H01L29/4236

Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a semiconductor substrate, a non-volatile memory cell, and a gate stack. The non-volatile memory cell is formed in the semiconductor substrate, and a top surface of the non-volatile memory cell is coplanar with or below a top surface of the semiconductor substrate. The gate stack is formed on the semiconductor substrate.

公开(公告)号：US11508783B2

公开(公告)日：2022-11-22

申请号：US17235785

申请日：2021-04-20

Applicant: United Microelectronics Corp.

Inventor： Chung-Tse Chen ,  Ko-Chi Chen ,  Tzu-Yun Chang

IPC: H01L27/24 ,  H01L45/00

Abstract: A method for fabricating memory device is provided. The method includes forming a transistor on a substrate. Further, a contact structure is formed on a source/drain region of the transistor. A conductive layer is formed on the contact structure. Four memory structures are formed on the conductive layer to form a quadrilateral structure.

公开(公告)号：US10090465B2

公开(公告)日：2018-10-02

申请号：US15359975

申请日：2016-11-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Ching Hsu ,  Liang Yi ,  Shen-De Wang ,  Ko-Chi Chen

IPC: H01L45/00

Abstract: A semiconductor device is provided, including a lower conducting layer formed above a substrate, an upper conducting layer, and a memory cell structure formed on the lower conducting layer (such as formed between the lower and upper conducting layers). The memory cell structure includes a bottom electrode formed on the lower conducting layer and electrically connected to the lower conducting layer, a transitional metal oxide (TMO) layer formed on the bottom electrode, a TMO sidewall oxides formed at sidewalls of the TMO layer, a top electrode formed on the TMO layer, and spacers formed on the bottom electrode. The upper conducting layer is formed on the top electrode and electrically connected to the top electrode.

公开(公告)号：US20180205013A1

公开(公告)日：2018-07-19

申请号：US15441261

申请日：2017-02-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Liang Yi ,  Chia-Ching Hsu ,  Shen-De Wang ,  Ko-Chi Chen

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L27/2436 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1683

Abstract: A method of forming a Resistive Random Access Memory (RRAM) includes the following steps. A first dielectric layer is formed on a first electrode layer. A second dielectric layer having a first trench is formed on the first dielectric layer. Spacers are formed beside sidewalls of the first trench. Apart of the first dielectric layer exposed by the spacers is removed, thereby forming a second trench in the first dielectric layer. A resistance switching material fills in the second trench. The second dielectric layer and the spacers are removed. A second electrode layer is formed on the resistance switching material and the first dielectric layer. The present invention also provides a RRAM formed by said method.

公开(公告)号：US20180175110A1

公开(公告)日：2018-06-21

申请号：US15884827

申请日：2018-01-31

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wen-Hsin Hsu ,  Ko-Chi Chen ,  Tzu-Yun Chang

IPC: H01L27/24 ,  H01L45/00 ,  H01L23/528

CPC classification number: H01L27/2463 ,  H01L23/528 ,  H01L27/2436 ,  H01L45/08 ,  H01L45/1226 ,  H01L45/1246 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/147 ,  H01L45/16 ,  H01L45/1608 ,  H05K999/99

Abstract: A semiconductor structure includes a memory unit structure. The memory unit structure includes a transistor, a first electrode, two second electrode, and two resistive random access memory (RRAM) elements. The first electrode and the two second electrodes are disposed in a horizontal plane. The first electrode is disposed between the two second electrodes. The first electrode and the two second electrodes are disposed in parallel. The first electrode is coupled to a source region of the transistor. One of the two RRAM elements is disposed between the first electrode and one of the two second electrodes. The other one of the two RRAM elements is disposed between the first electrode and the other one of the two second electrodes.

公开(公告)号：US09859335B1

公开(公告)日：2018-01-02

申请号：US15367690

申请日：2016-12-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Ching Hsu ,  Liang Yi ,  Shen-De Wang ,  Ko-Chi Chen

IPC: H01L29/00 ,  H01L27/24 ,  H01L29/24 ,  H01L45/00

CPC classification number: H01L27/2463 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1683

Abstract: A semiconductor device includes an interconnection formed above a substrate, and the interconnection comprising interconnect layers respectively buried in dielectric layers; a lower conducting layer formed above the substrate; a memory cell structure formed on the lower conducting layer and buried in one of the dielectric layers; an upper conducting layer formed on the memory cell structure. The memory cell structure includes a bottom electrode formed on and electrically connected to the lower conducting layer; a transitional metal oxide (TMO) layer formed on the bottom electrode; and a top electrode formed on the TMO layer, wherein the upper conducting layer is formed on the top electrode and electrically connected to the top electrode. Also, the lower conducting layer and the upper conducting layer are positioned in the different dielectric layers.

公开(公告)号：US09806255B1

公开(公告)日：2017-10-31

申请号：US15455142

申请日：2017-03-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Ching Hsu ,  Liang Yi ,  Shen-De Wang ,  Ko-Chi Chen

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/1233 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/12 ,  H01L45/124 ,  H01L45/1246 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1691

Abstract: A resistive random access memory includes a lower electrode, an upper electrode and a resistive layer between the lower electrode and the upper electrode, wherein the resistive layer includes a constant-resistance portion and a variable-resistance portion surrounding the constant-resistance portion.

公开(公告)号：US20140091383A1

公开(公告)日：2014-04-03

申请号：US14098290

申请日：2013-12-05

Applicant: United Microelectronics Corp.

Inventor： Ko-Chi Chen ,  Ping-Chia Shih ,  Chih-Ming Wang ,  Chi-Cheng Huang ,  Hsiang-Chen Lee

IPC: H01L29/792 ,  H01L29/78

CPC classification number: H01L29/792 ,  H01L27/11573 ,  H01L29/40117 ,  H01L29/665 ,  H01L29/66833 ,  H01L29/7833

Abstract: A method for fabricating a semiconductor device is described. A stacked gate dielectric is formed over a substrate, including a first dielectric layer, a second dielectric layer and a third dielectric layer from bottom to top. A conductive layer is formed on the stacked gate dielectric and then patterned to form a gate conductor. The exposed portion of the third and the second dielectric layers are removed with a selective wet cleaning step. S/D extension regions are formed in the substrate with the gate conductor as a mask. A first spacer is formed on the sidewall of the gate conductor and a portion of the first dielectric layer exposed by the first spacer is removed. S/D regions are formed in the substrate at both sides of the first spacer. A metal silicide layer is formed on the S/D regions.

Abstract translation: 对半导体装置的制造方法进行说明。 堆叠的栅极电介质形成在衬底上，包括从底部到顶部的第一介电层，第二电介质层和第三电介质层。 在堆叠的栅极电介质上形成导电层，然后将其图案化以形成栅极导体。 通过选择性湿式清洗步骤除去第三和第二介电层的暴露部分。 在栅极导体作为掩模的基板中形成S / D延伸区域。 在栅极导体的侧壁上形成第一间隔物，并且去除由第一间隔物露出的第一电介质层的一部分。 在第一间隔物的两侧的基板中形成S / D区域。 在S / D区域上形成金属硅化物层。

公开(公告)号：US20210242282A1

公开(公告)日：2021-08-05

申请号：US17235785

申请日：2021-04-20

Applicant: United Microelectronics Corp.

Inventor： Chung-Tse Chen ,  Ko-Chi Chen ,  Tzu-Yun Chang

IPC: H01L27/24 ,  H01L45/00

Abstract: A method for fabricating memory device is provided. The method includes forming a transistor on a substrate. Further, a contact structure is formed on a source/drain region of the transistor. A conductive layer is formed on the contact structure. Four memory structures are formed on the conductive layer to form a quadrilateral structure.