公开(公告)号：US20220254924A1

公开(公告)日：2022-08-11

申请号：US17171760

申请日：2021-02-09

Applicant: United Microelectronics Corp.

Inventor： Tseng Hsun Liu ,  Min-Hsuan Tsai ,  Ke-Feng Lin ,  Ming-Yen Liu ,  Wen-Chung Chang ,  Cherng-En Sun

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/10 ,  H01L29/66

Abstract: A transistor structure includes a substrate, having a gate region and a first trench in the substrate at a first side of the gate region. Further, a first gate insulating layer is disposed on a first portion of the gate region, opposite to the first trench. A second gate insulating layer is disposed on a second portion of the gate region and a first portion of the first trench abutting to the gate region, wherein the second gate insulating layer is thicker than the first gate insulating layer. A gate layer is disposed on the first and second gate insulating layers, having a downward protruding portion corresponding to the first trench. A first doped region is in the substrate at least under the first trench. A second doped region is in the substrate at a second side of the gate region.

公开(公告)号：US10903224B2

公开(公告)日：2021-01-26

申请号：US16685130

申请日：2019-11-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wen-Chung Chang ,  Tzu-Ping Chen

IPC: H01L27/11573 ,  H01L27/11568 ,  H01L27/11575 ,  H01L29/51 ,  H01L21/28

Abstract: A semiconductor device includes a semiconductor substrate, an isolation structure; a first gate dielectric layer and a first gate electrode. The isolation structure is formed in the semiconductor substrate to divide the semiconductor substrate at least into a first active region and a second active region. The first gate dielectric layer is disposed on the first active region, and has a plane top surface contacting to a sidewall of the isolation structure and forming an acute angle therewith. The first gate electrode stacked on the plane top surface.

公开(公告)号：US10096611B2

公开(公告)日：2018-10-09

申请号：US14807882

申请日：2015-07-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wen-Chung Chang ,  Sung-Bin Lin ,  Cherng-En Sun

IPC: H01L27/115 ,  H01L29/792 ,  H01L27/1157 ,  H01L29/423 ,  H01L29/06

Abstract: A trapping gate forming process includes the following. An oxide/nitride/oxide layer is formed on a substrate. A hard mask is formed to cover the oxide/nitride/oxide layer. The hard mask, the oxide/nitride/oxide layer and the substrate are patterned to form at least a trench in the hard mask, the oxide/nitride/oxide layer along a first direction. An isolation structure is formed in the trench. A first gate is formed across the oxide/nitride/oxide layer along a second direction orthogonal to the first direction. A flash cell formed by said process includes a substrate, a first gate and an oxide/nitride/oxide layer. The substrate contains at least an active area extending along a first direction. The first gate is disposed across the active area along a second direction orthogonal to the first direction, thereby intersecting an overlapping area. The oxide/nitride/oxide layer is disposed in the overlapping area between the first gate and the active area.

公开(公告)号：US09508835B2

公开(公告)日：2016-11-29

申请号：US13741399

申请日：2013-01-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wen-Chung Chang ,  Shen-De Wang ,  Ya-Huei Huang ,  Feng-Ji Tsai ,  Chien-Hung Chen

IPC: H01L27/115 ,  H01L29/66 ,  H01L29/792 ,  H01L29/423 ,  H01L21/28

CPC classification number: H01L29/66833 ,  H01L21/28282 ,  H01L27/11573 ,  H01L27/11575 ,  H01L29/4234 ,  H01L29/792

Abstract: A method for manufacturing a non-volatile memory structure includes providing a substrate having a memory region and a logic region defined thereon, masking the logic region while forming at least a first gate in the memory region, forming an oxide-nitride-oxide (ONO) structure under the first gate, forming an oxide structure covering the ONO structure on the substrate, masking the memory region while forming a second gate in the logic region, and forming a first spacer on sidewalls of the first gate and a second spacer on sidewalls of the second gate simultaneously.

Abstract translation: 一种用于制造非易失性存储器结构的方法包括提供具有存储区域和限定在其上的逻辑区域的衬底，在形成存储区域中的至少第一栅极的同时屏蔽逻辑区域，形成氧化物 - 氧化物 - 氧化物（ONO ）结构，在衬底上形成覆盖ONO结构的氧化物结构，在逻辑区域中形成第二栅极的同时掩蔽存储区域，以及在第一栅极的侧壁上形成第一间隔物，在侧壁上形成第二间隔物 的第二个门。

公开(公告)号：US20220328685A1

公开(公告)日：2022-10-13

申请号：US17852371

申请日：2022-06-29

Applicant: United Microelectronics Corp.

Inventor： Tseng Hsun Liu ,  Min-Hsuan Tsai ,  Ke-Feng Lin ,  Ming-Yen Liu ,  Wen-Chung Chang ,  Cherng-En Sun

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L29/423

Abstract: A method for fabricating a transistor includes providing a substrate, having a gate region and a first trench in the substate at a first side of the gate region; forming a first gate insulating layer, disposed on a first portion of the gate region, opposite to the first trench; forming a second gate insulating layer, disposed on a second portion of the gate region and a first portion of the first trench abutting to the gate region, wherein the second gate insulating layer is thicker than the first gate insulating layer; forming a gate layer, disposed on the first and second gate insulating layers, having a downward protruding portion corresponding to the first trench; forming a first doped region in the substrate at least under the first trench; and forming a second doped region in the substrate at a second side of the gate region.

公开(公告)号：US08837220B2

公开(公告)日：2014-09-16

申请号：US13741442

申请日：2013-01-15

Applicant: United Microelectronics Corp.

Inventor： Shen-De Wang ,  Wen-Chung Chang ,  Ya-Huei Huang ,  Feng-Ji Tsai ,  Chien-Hung Chen

IPC: G11C11/34 ,  G11C16/14 ,  H01L27/088 ,  G11C16/10

CPC classification number: G11C16/14 ,  G11C16/0475 ,  G11C16/10 ,  H01L21/28282 ,  H01L27/088 ,  H01L27/11565 ,  H01L27/11568

Abstract: A manipulating method of a nonvolatile memory is provided and comprises following steps. The nonvolatile memory having a plurality of memory cell is provided. Two adjacent memory cells correspond to one bit and comprise a substrate, a first and another first doping regions, a second doping region, a charge trapping layer, a control gate, a first bit line, a source line and a second bit line different from the first bit line. A first and a second channel are formed. The charge trapping layer is disposed on the first and the second channels. The two adjacent memory cells are programmed by following steps. A first positive and negative voltages are applied to the control gate between the first and the second doping regions and the control gate between the second and the another first doping regions, respectively. A first voltage is applied to the source line.

Abstract translation: 提供了一种非易失性存储器的操作方法，包括以下步骤。 提供具有多个存储单元的非易失性存储器。 两个相邻的存储器单元对应于一个位，并且包括基板，第一和第二第一掺杂区域，第二掺杂区域，电荷俘获层，控制栅极，第一位线，源极线和与 第一个位线。 形成第一和第二通道。 电荷捕获层设置在第一和第二通道上。 通过以下步骤对相邻的两个存储单元进行编程。 第一正电压和负电压分别施加到第一和第二掺杂区域之间的控制栅极以及第二和第二掺杂区域之间的控制栅极。 第一个电压被施加到源极线。

公开(公告)号：US20140197472A1

公开(公告)日：2014-07-17

申请号：US13741399

申请日：2013-01-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wen-Chung Chang ,  Shen-De Wang ,  Ya-Huei Huang ,  Feng-Ji Tsai ,  Chien-Hung Chen

IPC: H01L29/66 ,  H01L29/792

CPC classification number: H01L29/66833 ,  H01L21/28282 ,  H01L27/11573 ,  H01L27/11575 ,  H01L29/4234 ,  H01L29/792

Abstract: A method for manufacturing a non-volatile memory structure includes providing a substrate having a memory region and a logic region defined thereon, masking the logic region while forming at least a first gate in the memory region, forming an oxide-nitride-oxide (ONO) structure under the first gate, forming an oxide structure covering the ONO structure on the substrate, masking the memory region while forming a second gate in the logic region, and forming a first spacer on sidewalls of the first gate and a second spacer on sidewalls of the second gate simultaneously.

Abstract translation: 一种用于制造非易失性存储器结构的方法包括提供具有存储区域和限定在其上的逻辑区域的衬底，在形成存储区域中的至少第一栅极的同时屏蔽逻辑区域，形成氧化物 - 氧化物 - 氧化物（ONO ）结构，在衬底上形成覆盖ONO结构的氧化物结构，在逻辑区域中形成第二栅极的同时掩蔽存储区域，以及在第一栅极的侧壁上形成第一间隔物，在侧壁上形成第二间隔物 的第二个门。