公开(公告)号：US12148809B2

公开(公告)日：2024-11-19

申请号：US17583225

申请日：2022-01-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hsien Huang ,  Yu-Tse Kuo ,  Shu-Ru Wang ,  Chien-Hung Chen ,  Li-Ping Huang ,  Chun-Yen Tseng

IPC: H01L29/423 ,  G11C5/06 ,  G11C11/412 ,  H01L29/78 ,  H10B10/00

Abstract: The present invention provides a layout pattern of static random access memory, comprising a PU1 (first pull-up transistor), a PU2 (second pull-up transistor), a PD1A (first pull-down transistor), a PD1B (second pull-down transistor), a PD2A (third pull-down transistor), a PD2B (fourth pull-down transistor), a PG1A (first access transistor), a PG1B (second access transistor), a PG2A (third access transistor) and a PG2B (fourth access transistor) located on the substrate. The PD1A and the PD1B are connected in parallel with each other, the PD2A and the PD2B are connected in parallel with each other, wherein the gate structures include a first J-shaped gate structure, and the first J-shaped gate structure is an integrally formed structure.

公开(公告)号：US20230238058A1

公开(公告)日：2023-07-27

申请号：US17680264

申请日：2022-02-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Wen Wang ,  Chien-Hung Chen ,  Chia-Hui Huang ,  Jen-Yang Hsueh ,  Ling-Hsiu Chou ,  Chih-Yang Hsu

IPC: G11C11/56 ,  G11C16/34 ,  G11C16/10

CPC classification number: G11C11/5628 ,  G11C16/3427 ,  G11C16/10 ,  G11C16/3459 ,  G11C16/0483

Abstract: When programming an MLC memory device, the disturb characteristics of a program block having multiple memory cells are measured, and the threshold voltage variations of the multiple memory cells are then acquired based on the disturb characteristics of the program block. Next, multiple initial program voltage pulses are provided according to a predetermined signal level, and multiple compensated program voltage pulses are provided by adjusting the multiple initial program voltage pulses. Last, the multiple compensated program voltage pulses are outputted to the program block for programming the multiple memory cells to the predetermined signal level.

公开(公告)号：US11538813B2

公开(公告)日：2022-12-27

申请号：US16923117

申请日：2020-07-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Chun-Hsien Lin ,  Chien-Hung Chen

IPC: H01L27/11 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/417 ,  H01L21/285 ,  H01L29/45

Abstract: A method for fabricating a static random access memory (SRAM) includes the steps of: forming a gate structure on a substrate; forming an epitaxial layer adjacent to the gate structure; forming a first interlayer dielectric (ILD) layer around the gate structure; transforming the gate structure into a metal gate; forming a contact hole exposing the epitaxial layer, forming a barrier layer in the contact hole, forming a metal layer on the barrier layer, and then planarizing the metal layer and the barrier layer to form a contact plug. Preferably, a bottom portion of the barrier layer includes a titanium rich portion and a top portion of the barrier layer includes a nitrogen rich portion.

公开(公告)号：US20220344321A1

公开(公告)日：2022-10-27

申请号：US17348784

申请日：2021-06-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kun-Yuan Wu ,  Wei-Jen Wang ,  Chien-Fu Chen ,  Chen-Hsien Hsu ,  Chien-Hung Chen ,  Chun-Hsien Lin

IPC: H01L27/02

Abstract: An integrated circuit layout includes a first standard cell and a second standard cell. The first standard cell includes first gate lines arranged along a first direction and extending along a second direction. The second standard cell abuts to one side of the first standard cell along the second direction and includes second gate lines arranged along the first direction and extending along the second direction. A first gate line width of the first gate lines and a second gate line width of the second gate lines are different. A first cell width of the first standard cell and a second cell width of the second standard cell are integral multiples of a default gate line pitch of the first gate lines and the second gate lines. At least some of the second gate lines and at least some of the first gate lines are aligned along the second direction.

公开(公告)号：US10373861B1

公开(公告)日：2019-08-06

申请号：US16026077

申请日：2018-07-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chi-Ying Hsieh ,  Chih-Jung Chen ,  Chien-Hung Chen ,  Chih-Yueh Li ,  Cheng-Pu Chiu ,  Shih-Min Lu ,  Yung-Sung Lin

IPC: H01L21/76 ,  H01L21/762 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L29/08

Abstract: A semiconductor structure includes a substrate having a plurality of fin structures thereon, an isolation oxide structure in the substrate between adjacent two of the plurality of fin structures, a gate disposed on the plurality of fin structures, a gate dielectric layer disposed between the plurality of fin structures and the gate, and a source/drain doped region in each of the plurality of fin structures. The isolation oxide structure has a concave, curved top surface.

公开(公告)号：US20190237460A1

公开(公告)日：2019-08-01

申请号：US16380953

申请日：2019-04-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tzu-Ping Chen ,  Chien-Hung Chen

IPC: H01L27/06 ,  H01L27/11543 ,  H01L27/11541 ,  H01L29/788 ,  H01L21/285 ,  H01L29/423 ,  H01L21/28 ,  H01L21/311 ,  H01L29/66

CPC classification number: H01L27/0629 ,  H01L21/31144 ,  H01L27/11541 ,  H01L27/11543 ,  H01L29/40114 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7881

Abstract: A method for fabricating a semiconductor device includes the steps of providing a semiconductor substrate; forming a tunnel dielectric on the semiconductor substrate; forming a floating gate on the tunnel dielectric; forming an insulation layer conformally disposed on the top surface and the sidewall surface of the floating gate; forming a control gate disposed on the insulation layer and the floating gate; and forming a spacer continuously distributed on the sidewall surfaces of the floating gate and the control gate, where the spacer overlaps portions of the top surface of the floating gate

公开(公告)号：US10177231B2

公开(公告)日：2019-01-08

申请号：US15797011

申请日：2017-10-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chien-Hung Chen ,  Shih-Hsien Huang ,  Yu-Ru Yang ,  Huai-Tzu Chiang ,  Hao-Ming Lee ,  Sheng-Hao Lin ,  Cheng-Tzung Tsai ,  Chun-Yuan Wu

IPC: H01L21/02 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78 ,  H01L21/306 ,  H01L29/165 ,  H01L21/3065

Abstract: A semiconductor device comprises a semiconductor substrate and a semiconductor fin. The semiconductor substrate has an upper surface and a recess extending downwards into the semiconductor substrate from the upper surface. The semiconductor fin is disposed in the recess and extends upwards beyond the upper surface, wherein the semiconductor fin is directly in contact with semiconductor substrate, so as to form at least one semiconductor hetero-interface on a sidewall of the recess.

公开(公告)号：US20180294359A1

公开(公告)日：2018-10-11

申请号：US15591031

申请日：2017-05-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tzu-Ping Chen ,  Chien-Hung Chen

IPC: H01L29/788 ,  H01L27/11536 ,  H01L21/285 ,  H01L21/311 ,  H01L27/06

CPC classification number: H01L27/0629 ,  H01L21/28273 ,  H01L21/28518 ,  H01L27/11541 ,  H01L27/11543 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7881

Abstract: A semiconductor device includes a semiconductor substrate, a tunnel dielectric disposed on the semiconductor substrate, a floating gate disposed on the tunnel dielectric, a control gate disposed on the floating gate, and an insulation layer disposed between the floating gate and the control gate. The semiconductor device further includes a spacer continuously distributed on the sidewall surfaces of the floating gate and the control gate, and the spacer overlaps portions of the top surface of the floating gate.

公开(公告)号：US10090308B1

公开(公告)日：2018-10-02

申请号：US15498464

申请日：2017-04-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chien-Hung Chen ,  Meng-Ping Chuang ,  Hsueh-Hao Shih

IPC: H01L27/11 ,  H01L27/02 ,  H01L27/092 ,  H01L23/528 ,  G11C11/417

Abstract: A semiconductor memory device having a memory cell including a plurality of memory cells, a first P-type well region, a second P-type well region, and an N-type well region disposed between the first P-Type well region and the second P-type well region. The semiconductor memory element defines a plurality of first regions, a plurality of second regions, a plurality of third regions, and a plurality of fourth regions, and each first region includes the memory cell. Each second region, each third region and each fourth region include a voltage contact to provide a voltage to the first P-type well region, the second P-type well region, and the N-type well region. The first region to the fourth region do not overlap with each other.

公开(公告)号：US09898569B2

公开(公告)日：2018-02-20

申请号：US14852635

申请日：2015-09-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hsien Wu ,  Chen-Hsien Hsu ,  Wei-Jen Wang ,  Chien-Fu Chen ,  Chien-Hung Chen

IPC: H01L21/70 ,  G06F17/50 ,  H01L27/02

CPC classification number: G06F17/5072 ,  H01L21/823437 ,  H01L27/0207 ,  H01L27/088

Abstract: A method for designing a semiconductor layout structure includes following steps. A first active feature group including at least a first active feature is received, and the first active feature includes a first channel length. A pair of first dummy features is introduced to form a first cell pattern. The first dummy features include a first dummy width. A first spacing width is defined between the first active feature group and one of the first dummy features and a third spacing width is defined between the first active feature group and the other first dummy feature. The first cell pattern includes a first cell width and a first poly pitch, and the first cell width is a multiple of the first pitch. The receiving of the first active feature group and the introducing of the first dummy features are performed in by at least a computer-aided design tool.