公开(公告)号：US10541309B2

公开(公告)日：2020-01-21

申请号：US15853867

申请日：2017-12-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Fan Li ,  Kuo-Chin Hung ,  Wen-Yi Teng ,  Ti-Bin Chen

IPC: H01L29/417 ,  H01L29/49 ,  H01L29/423 ,  H01L29/161 ,  H01L29/78 ,  H01L29/66 ,  H01L21/311

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes first and second metal gates on a substrate with a gap therebetween. The first metal gate has a first sidewall, and the second metal gate has a second sidewall directly facing the first sidewall. A contact etch stop layer (CESL) is disposed within the gap and extends along the first and second sidewalls. The CESL has a first top portion adjacent to a top surface of the first metal gate and a second top portion adjacent to a top surface of the second metal gate. The first top portion and the second top portion have a trapezoid cross-sectional profile. A first sidewall spacer is disposed on the first sidewall and between the CESL and the first metal gate. A second sidewall spacer is disposed on the second sidewall and between the CESL and the second metal gate.

公开(公告)号：US09343573B2

公开(公告)日：2016-05-17

申请号：US14557469

申请日：2014-12-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Chien Liu ,  Tzu-Chin Wu ,  Yu-Shu Lin ,  Jei-Ming Chen ,  Wen-Yi Teng

IPC: H01L29/78 ,  H01L21/8234 ,  H01L21/324 ,  H01L21/02 ,  H01L21/768 ,  H01L29/66 ,  H01L21/8238

CPC classification number: H01L29/7843 ,  H01L21/02164 ,  H01L21/324 ,  H01L21/76828 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/823412 ,  H01L21/823807 ,  H01L21/823864 ,  H01L29/6653

Abstract: A method of fabrication a transistor device with a non-uniform stress layer including the following processes. First, a semiconductor substrate having a first transistor region is provided. A low temperature deposition process is carried out to form a first tensile stress layer on a transistor within the first transistor region, wherein a temperature of the low temperature deposition process is lower than 300 degree Celsius (° C.). Then, a high temperature annealing process is performed, wherein a temperature of the high temperature annealing process is at least 150° C. higher than a temperature of the low temperature deposition process. Finally, a second tensile stress layer is formed on the first tensile stress layer, wherein the first tensile stress layer has a tensile stress lower than a tensile stress of the second tensile stress layer.

Abstract translation: 一种制造具有不均匀应力层的晶体管器件的方法，包括以下过程。 首先，提供具有第一晶体管区域的半导体衬底。 进行低温沉积工艺以在第一晶体管区域内的晶体管上形成第一拉伸应力层，其中低温沉积工艺的温度低于300摄氏度（℃）。 然后，进行高温退火处理，其中高温退火工艺的温度比低温沉积工艺的温度高至少150℃。 最后，在第一拉伸应力层上形成第二拉伸应力层，其中第一拉伸应力层的拉伸应力低于第二拉伸应力层的拉伸应力。

公开(公告)号：US11031477B2

公开(公告)日：2021-06-08

申请号：US16701122

申请日：2019-12-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Fan Li ,  Kuo-Chin Hung ,  Wen-Yi Teng ,  Ti-Bin Chen

IPC: H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L29/49 ,  H01L29/423 ,  H01L21/311 ,  H01L29/161 ,  H01L29/165

Abstract: A first dummy gate and a second dummy gate are formed on a substrate with a gap between the first and second dummy gates. The first dummy gate has a first sidewall. The second dummy gate has a second sidewall directly facing the first sidewall. A first sidewall spacer is disposed on the first sidewall. A second sidewall spacer is disposed on the second sidewall. A contact etch stop layer is deposited on the first and second dummy gates and on the first and second sidewall spacers. The contact etch stop layer is subjected to a tilt-angle plasma etching process to trim a corner portion of the contact etch stop layer. An inter-layer dielectric layer is then deposited on the contact etch stop layer and into the gap.

公开(公告)号：US20160020139A1

公开(公告)日：2016-01-21

申请号：US14478609

申请日：2014-09-05

Applicant: United Microelectronics Corp.

Inventor： Wen-Yi Teng ,  Yuh-Min Lin ,  Chih-Chien Liu ,  Chieh-Wen Lo

IPC: H01L21/762 ,  H01L23/58 ,  H01L21/02 ,  H01L29/06

CPC classification number: H01L21/76224 ,  H01L21/02164 ,  H01L21/02219 ,  H01L21/02271 ,  H01L21/02326 ,  H01L21/02337 ,  H01L21/67196 ,  H01L21/67201 ,  H01L21/67742 ,  H01L21/67766 ,  H01L21/762 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A gap-filling dielectric layer, method for fabricating the same and applications thereof are disclosed. A silicon-containing dielectric layer is firstly deposited on a substrate. The silicon-containing dielectric layer is then subjected to a curing process, an in-situ wetting treatment and an annealing process in sequence, whereby a gap-filling dielectric layer with a nitrogen atom density less than 1×1022 atoms/cm3 is formed.

Abstract translation: 公开了间隙填充介电层，其制造方法及其应用。 首先在基板上沉积含硅介电层。 然后对含硅电介质层进行固化处理，原位润湿处理和退火处理，由此形成氮原子密度小于1×1022原子/ cm3的间隙填充介电层。

公开(公告)号：US08927388B2

公开(公告)日：2015-01-06

申请号：US13677318

申请日：2012-11-15

Applicant: United Microelectronics Corp.

Inventor： Jei-Ming Chen ,  Wen-Yi Teng ,  Chia-Lung Chang ,  Chih-Chien Liu

IPC: H01L21/76 ,  H01L21/762 ,  H01L21/3105 ,  H01L21/768 ,  H01L21/02

CPC classification number: H01L21/76224 ,  H01L21/02164 ,  H01L21/3105 ,  H01L21/76229 ,  H01L21/76819 ,  H01L21/76826 ,  H01L21/76837

Abstract: A method of fabricating a dielectric layer includes the following steps. At first, a dielectric layer is formed on a substrate, and a chemical mechanical polishing (CMP) process is performed on the dielectric layer. Subsequently, a surface treatment process is performed on the dielectric layer after the chemical mechanical polishing process, and the surface treatment process includes introducing an oxygen plasma.

Abstract translation: 制造介电层的方法包括以下步骤。 首先，在基板上形成电介质层，对电介质层进行化学机械研磨（CMP）处理。 随后，在化学机械抛光工艺之后对电介质层进行表面处理工艺，并且表面处理工艺包括引入氧等离子体。