公开(公告)号：US07199007B2

公开(公告)日：2007-04-03

申请号：US10806052

申请日：2004-03-22

申请人： Uway Tseng ,  Wenpin Lu ,  Chun-Lien Su

发明人： Uway Tseng ,  Wenpin Lu ,  Chun-Lien Su

IPC分类号： H01L21/8247

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L29/42324 ,  Y10S438/954

摘要： A method is provided for forming a non-volatile memory device. The method includes forming a stacked structure including a tunnel oxide layer, a floating gate, a thin oxide layer, and a control gate on a semiconductor substrate. Etching is used to define the sidewalls of the stacked structure. Dopants are implanted into exposed areas of the substrate to form source and drain regions within the substrate adjacent to the stacked structure. A liner dielectric layer is formed on the sidewalls of the stacked structure to patch the etching damage. Thereafter, a nitride barrier layer is formed on the liner dielectric layer, and an oxide spacer is formed on the nitride barrier layer. The nitride barrier layer can trap negative charge and thus act as a relatively high barrier at the tunneling oxide edge. Therefore, the threshold voltage difference between the initial erase of the memory device and the erase after many cycles is reduced.

公开(公告)号：US06511907B1

公开(公告)日：2003-01-28

申请号：US09983565

申请日：2001-10-25

申请人： Jung-Yu Hsieh ,  Uway Tseng

发明人： Jung-Yu Hsieh ,  Uway Tseng

IPC分类号： H01L214763

CPC分类号： H01L21/7684 ,  H01L21/76819

摘要： A method for forming a low loss dielectric layer in the tungsten chemical mechanic grinding process is disclosed. After forming a dielectric layer on the semiconductor substrate and smoothing the dielectric layer as an inner dielectric layer, a stop layer of undoped silicon dioxide, organ spin on glass, or silicon oxygen nitride are coated thereon. After process of plug lithographic and etching, a barrier layer of tungsten plug and metal tungsten are deposited sequentially. Finally, the surplus tungsten metal layer on the surface of a dielectric layer is removed by chemical mechanic grinding process until the stop layer is exposed. In the present invention, the stop layer is used to repair the scratches or defects generated from the smoothness in the chemical mechanic grinding process. Furthermore, in the tungsten chemical mechanic grinding process, it can assure that the inner dielectric layer will not be ground so that the object of low loss is achieved.

摘要翻译： 公开了一种在钨化学机械研磨工艺中形成低损耗介电层的方法。 在半导体衬底上形成电介质层并使作为内部电介质层的电介质层平坦化之后，涂覆未掺杂二氧化硅的停止层，玻璃上的器件自旋或氮氧化硅。 在插件光刻和蚀刻过程之后，依次沉积钨插件和金属钨的阻挡层。 最后，通过化学机械研磨过程去除电介质层表面上的剩余钨金属层，直到暴露出停止层。 在本发明中，停止层用于修复在化学机械研磨过程中由平滑度产生的划痕或缺陷。 此外，在钨化学机械研磨工艺中，可以确保内部电介质层不被研磨，从而实现低损耗的目的。

公开(公告)号：US08716871B2

公开(公告)日：2014-05-06

申请号：US13397488

申请日：2012-02-15

申请人： Uway Tseng ,  Shu-Hui Su

发明人： Uway Tseng ,  Shu-Hui Su

IPC分类号： H01L23/485 ,  H01L21/768

CPC分类号： H01L24/05 ,  H01L21/76801 ,  H01L21/76816 ,  H01L21/76837 ,  H01L21/7684 ,  H01L21/76877 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48463 ,  H01L2924/01015 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2924/00014

摘要： A semiconductor device that includes a first metal layer component formed over a substrate. The semiconductor device includes a via formed over the first metal layer component. The via has a recessed shape. The semiconductor device includes a second metal layer component formed over the via. The semiconductor device includes a first dielectric layer component formed over the substrate. The first dielectric layer component is located adjacent to, and partially over, the first metal layer component. The first dielectric layer component contains fluorine. The semiconductor device includes a second dielectric layer component formed over the first dielectric layer component. The first dielectric layer component and the second dielectric layer component are each located adjacent to the via. The second dielectric layer component is free of fluorine.

摘要翻译： 一种半导体器件，包括在衬底上形成的第一金属层组件。 半导体器件包括形成在第一金属层部件上的通孔。 通孔具有凹陷形状。 半导体器件包括在通孔上形成的第二金属层元件。 半导体器件包括形成在衬底上的第一介电层组件。 第一介电层组件位于第一金属层组件附近并部分地位于第一金属层组件上。 第一介电层组分含氟。 半导体器件包括形成在第一介电层部件上的第二介电层部件。 第一电介质层组分和第二介电层组分各自位于与通孔相邻的位置。 第二介电层组分不含氟。

公开(公告)号：US20110156217A1

公开(公告)日：2011-06-30

申请号：US12651322

申请日：2009-12-31

申请人： Alex Kalnitsky ,  Hsiao-Chin Tuan ,  Liang-Kai Han ,  Uway Tseng ,  Yuan-Chih Hsieh ,  Hung-Hua Lin

发明人： Alex Kalnitsky ,  Hsiao-Chin Tuan ,  Liang-Kai Han ,  Uway Tseng ,  Yuan-Chih Hsieh ,  Hung-Hua Lin

IPC分类号： H01L23/58 ,  H01L21/78

CPC分类号： H01L29/66712 ,  H01L21/78 ,  H01L23/562 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming a support structure for supporting and handling a semiconductor wafer containing vertical FETs formed at the front surface thereof is provided. In one embodiment, a semiconductor wafer is provided having a front surface and a rear surface, wherein the front surface comprises one or more dies separated by dicing lines. The wafer is thinned to a predetermined thickness. A plurality of patterned metal features are formed on a thinned rear surface to provide support for the wafer, wherein each of the plurality of patterned metal features covers substantially one die, leaving the dicing lines substantially uncovered. The wafer is thereafter diced along the dicing lines to separate the one or more dies for later chip packaging.

摘要翻译： 提供一种形成用于支撑和处理包含形成在其前表面上的垂直FET的半导体晶片的支撑结构的方法。 在一个实施例中，提供具有前表面和后表面的半导体晶片，其中前表面包括由切割线分开的一个或多个裸片。 将晶片减薄至预定厚度。 多个图案化的金属特征形成在薄的后表面上以提供对晶片的支撑，其中多个图案化的金属特征中的每一个基本上覆盖一个管芯，使切割线基本上不被覆盖。 然后，晶片沿着切割线切割，以分离一个或多个模具用于稍后的芯片封装。

公开(公告)号：US07400011B2

公开(公告)日：2008-07-15

申请号：US11715217

申请日：2007-03-06

申请人： Uway Tseng ,  Wenpin Lu ,  Chun-Lien Su

发明人： Uway Tseng ,  Wenpin Lu ,  Chun-Lien Su

IPC分类号： H01L29/788

CPC分类号： H01L29/66825 ,  H01L29/2003 ,  H01L29/42324 ,  H01L29/7881

摘要： A method is provided for forming a non-volatile memory device. The method includes forming a stacked structure including a tunnel oxide layer, a floating gate, a thin oxide layer, and a control gate on a semiconductor substrate. Etching is used to define the sidewalls of the stacked structure. Dopants are implanted into exposed areas of the substrate to form source and drain regions within the substrate adjacent to the stacked structure. A liner dielectric layer is formed on the sidewalls of the stacked structure to patch the etching damage. Thereafter, a nitride barrier layer is formed on the liner dielectric layer, and an oxide spacer is formed on the nitride barrier layer. The nitride barrier layer can trap negative charge and thus act as a relatively high barrier at the tunneling oxide edge. Therefore, the threshold voltage difference between the initial erase of the memory device and the erase after many cycles is reduced.

摘要翻译： 提供了一种用于形成非易失性存储器件的方法。 该方法包括在半导体衬底上形成包括隧道氧化物层，浮置栅极，薄氧化物层和控制栅极的堆叠结构。 蚀刻用于限定堆叠结构的侧壁。 将掺杂剂注入到衬底的暴露区域中，以在与衬底结构相邻的衬底内形成源区和漏区。 衬垫介电层形成在层叠结构的侧壁上以补偿蚀刻损伤。 此后，在衬垫电介质层上形成氮化物阻挡层，在氮化物阻挡层上形成氧化物间隔物。 氮化物阻挡层可以捕获负电荷，并因此在隧道氧化物边缘处起到较高的阻挡作用。 因此，存储器件的初始擦除与许多周期之后的擦除之间的阈值电压差减小。

公开(公告)号：US20070020877A1

公开(公告)日：2007-01-25

申请号：US11186360

申请日：2005-07-21

申请人： Uway Tseng ,  Ching-Yu Chang

发明人： Uway Tseng ,  Ching-Yu Chang

IPC分类号： H01L21/76

CPC分类号： H01L21/76224

摘要： A shallow trench isolation structure has a trench formed in a substrate, a silicon oxynitride layer conformally formed on the sidewalls and bottom of the trench, and a high density plasma (HDP) oxide layer substantially filling the trench.

摘要翻译： 浅沟槽隔离结构具有在衬底中形成的沟槽，保形地形成在沟槽的侧壁和底部上的氧氮化硅层和基本上填充沟槽的高密度等离子体（HDP）氧化物层。

公开(公告)号：US06960506B2

公开(公告)日：2005-11-01

申请号：US10714128

申请日：2003-11-13

申请人： Hung-Yu Chiu ,  Ming-Shang Chen ,  Wenpin Lu ,  Uway Tseng

发明人： Hung-Yu Chiu ,  Ming-Shang Chen ,  Wenpin Lu ,  Uway Tseng

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8239 ,  H01L21/8247 ,  H01L27/115

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L27/115

摘要： A method of forming a memory device having a self-aligned contact is described. The method includes providing a substrate having a floating gate dielectric layer formed thereon, forming a floating poly gate layer on the floating gate dielectric layer, forming a first silicon nitride layer on the floating poly gate layer, and forming a patterned photoresist layer on the first silicon nitride layer. The method further includes etching the first silicon nitride layer and the floating poly gate layer using the patterned photoresist layer as an etch mask, forming an oxide layer over the exposed etched areas, removing the patterned photoresist layer and the first silicon nitride layer to expose the floating poly gate layer, forming poly spaces in the floating poly gate layer, and depositing a second silicon nitride layer over the poly spaces of the floating poly gate layer to form a self-aligned contact.

摘要翻译： 描述形成具有自对准接触的存储器件的方法。 该方法包括提供具有形成在其上的浮置栅极介电层的衬底，在浮置栅极电介质层上形成浮动多晶硅栅极层，在浮动多晶硅层上形成第一氮化硅层，并在第一层上形成图案化光致抗蚀剂层 氮化硅层。 该方法还包括使用图案化的光致抗蚀剂层作为蚀刻掩模蚀刻第一氮化硅层和浮动多晶硅层，在暴露的蚀刻区域上形成氧化物层，去除图案化的光致抗蚀剂层和第一氮化硅层， 浮动多晶硅栅极层，在浮动多晶硅层中形成多个空间，以及在浮动多晶硅栅极层的多晶硅间隔上沉积第二个氮化硅层以形成自对准的接触。

公开(公告)号：US06734098B2

公开(公告)日：2004-05-11

申请号：US10064699

申请日：2002-08-08

申请人： Uway Tseng ,  Hung-Yu Chiu

发明人： Uway Tseng ,  Hung-Yu Chiu

IPC分类号： H01L214763

CPC分类号： H01L21/28518

摘要： A fabrication method for a cobalt-salicide contact is described. A deep sub-micron contact opening is formed on a substrate. A silicon nitride spacer is further formed on the contact sidewall. A cobalt layer is further deposited in the contact opening, followed by sequentially forming an ionized metal plasma titanium layer and a chemical vapor deposited titanium nitride layer. A first rapid thermal process is performed and a wet etching is performed to remove the titanium/titanium nitride layer. A second rapid thermal process is performed, followed by filling the contact opening with a conductive layer.

公开(公告)号：US06548425B2

公开(公告)日：2003-04-15

申请号：US09851570

申请日：2001-05-10

申请人： Kent Kuohua Chang ,  Uway Tseng

发明人： Kent Kuohua Chang ,  Uway Tseng

IPC分类号： H01L2131

CPC分类号： H01L21/02238 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02271 ,  H01L21/02332 ,  H01L21/02337 ,  H01L21/28282 ,  H01L21/3144 ,  H01L27/11568 ,  Y10S438/954

摘要： The present invention fabricates an oxide-nitride-oxide (ONO) layer of an NROM. A first oxide layer is formed on the surface of the substrate of a semiconductor wafer. Then two CVD processes are performed to respectively form a first nitride layer and a second nitride layer on the surface of the first oxide layer, and the boundary between the second nitride layer and the first nitride layer is so forming an interface. Thereafter, a second oxide layer is formed on the surface of the second nitride layer completing the process of manufacturing the ONO layer. The second nitride layer and the first nitride layer are used as a floating gate of the NROM, and the interface is used as a deep charge trapping center to improve the charge trapping efficiency, and furthermore, to improve the endurance and reliability of the NROM.

公开(公告)号：US20130207276A1

公开(公告)日：2013-08-15

申请号：US13397488

申请日：2012-02-15

申请人： Uway Tseng ,  Shu-Hui Su

发明人： Uway Tseng ,  Shu-Hui Su

IPC分类号： H01L23/485 ,  H01L21/768

CPC分类号： H01L24/05 ,  H01L21/76801 ,  H01L21/76816 ,  H01L21/76837 ,  H01L21/7684 ,  H01L21/76877 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48463 ,  H01L2924/01015 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2924/00014

摘要： The present disclosure provides a semiconductor device. The semiconductor device includes a first metal layer component formed over a substrate. The semiconductor device includes a via formed over the first metal layer component. The via has a recessed shape. The semiconductor device includes a second metal layer component formed over the via. The semiconductor device includes a first dielectric layer component formed over the substrate. The first dielectric layer component is located adjacent to, and partially over, the first metal layer component. The first dielectric layer component contains fluorine. The semiconductor device includes a second dielectric layer component formed over the first dielectric layer component. The first dielectric layer component and the second dielectric layer component are each located adjacent to the via. The second dielectric layer component is free of fluorine.

摘要翻译： 本发明提供一种半导体器件。 半导体器件包括形成在衬底上的第一金属层部件。 半导体器件包括形成在第一金属层部件上的通孔。 通孔具有凹陷形状。 半导体器件包括在通孔上形成的第二金属层元件。 半导体器件包括形成在衬底上的第一介电层组件。 第一介电层组件位于第一金属层组件附近并部分地位于第一金属层组件上。 第一介电层组分含氟。 半导体器件包括形成在第一介电层部件上的第二介电层部件。 第一电介质层组分和第二介电层组分各自位于与通孔相邻的位置。 第二介电层组分不含氟。