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27 条记录 (耗时 0.017 秒)

    Method for forming a low loss dielectric layer in the tungsten chemical mechanic grinding process
    1.
    发明授权
    Method for forming a low loss dielectric layer in the tungsten chemical mechanic grinding process 有权
    在钨化学机械研磨过程中形成低损耗介电层的方法

    公开(公告)号：US06511907B1

    公开(公告)日：2003-01-28

    申请号：US09983565

    申请日：2001-10-25

    申请人： Jung-Yu Hsieh ,  Uway Tseng

    发明人： Jung-Yu Hsieh ,  Uway Tseng

    IPC分类号： H01L214763

    CPC分类号： H01L21/7684 ,  H01L21/76819

    摘要： A method for forming a low loss dielectric layer in the tungsten chemical mechanic grinding process is disclosed. After forming a dielectric layer on the semiconductor substrate and smoothing the dielectric layer as an inner dielectric layer, a stop layer of undoped silicon dioxide, organ spin on glass, or silicon oxygen nitride are coated thereon. After process of plug lithographic and etching, a barrier layer of tungsten plug and metal tungsten are deposited sequentially. Finally, the surplus tungsten metal layer on the surface of a dielectric layer is removed by chemical mechanic grinding process until the stop layer is exposed. In the present invention, the stop layer is used to repair the scratches or defects generated from the smoothness in the chemical mechanic grinding process. Furthermore, in the tungsten chemical mechanic grinding process, it can assure that the inner dielectric layer will not be ground so that the object of low loss is achieved.

    摘要翻译： 公开了一种在钨化学机械研磨工艺中形成低损耗介电层的方法。 在半导体衬底上形成电介质层并使作为内部电介质层的电介质层平坦化之后，涂覆未掺杂二氧化硅的停止层，玻璃上的器件自旋或氮氧化硅。 在插件光刻和蚀刻过程之后，依次沉积钨插件和金属钨的阻挡层。 最后，通过化学机械研磨过程去除电介质层表面上的剩余钨金属层，直到暴露出停止层。 在本发明中，停止层用于修复在化学机械研磨过程中由平滑度产生的划痕或缺陷。 此外，在钨化学机械研磨工艺中，可以确保内部电介质层不被研磨，从而实现低损耗的目的。

    Dual damascene with via liner
    4.
    发明授权
    Dual damascene with via liner 有权
    双镶嵌带通孔衬垫

    公开(公告)号：US07884013B2

    公开(公告)日：2011-02-08

    申请号：US12154823

    申请日：2008-05-27

    申请人： Uway Tseng ,  Alex Huang ,  Kun-Szu Liu

    发明人： Uway Tseng ,  Alex Huang ,  Kun-Szu Liu

    IPC分类号： H01L21/4763

    CPC分类号： H01L23/5226 ,  H01L21/76808 ,  H01L21/76831 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2221/1031 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A dual damascene structure with improved profiles and reduced defects and method of forming the same, the method including forming a first dielectric over a conductive area; forming a first dielectric insulator over the first dielectric; forming a first opening in the first dielectric insulator; lining the opening with a second dielectric; forming a second dielectric insulator over the first dielectric insulator; forming a second opening in the second dielectric insulator overlying and communicating with the first opening; and, filling the first and second openings with a conductive material to electrically communicate with the conductive area.

    摘要翻译： 具有改进的轮廓和减少的缺陷的双镶嵌结构及其形成方法，所述方法包括在导电区域上形成第一电介质; 在所述第一电介质上形成第一电介质绝缘体; 在所述第一介电绝缘体中形成第一开口; 用第二电介质衬里开口; 在所述第一绝缘绝缘体上形成第二电介质绝缘体; 在所述第二绝缘绝缘体中形成第二开口，所述第二开口覆盖并与所述第一开口连通; 并且用导电材料填充第一和第二开口以与导电区域电连通。

    SHALLOW TRENCH ISOLATION STRUCTURE AND METHOD OF FABRICATING THE SAME
    5.
    发明申请
    SHALLOW TRENCH ISOLATION STRUCTURE AND METHOD OF FABRICATING THE SAME 审中-公开
    浅层隔离结构及其制造方法

    公开(公告)号：US20070178664A1

    公开(公告)日：2007-08-02

    申请号：US11697751

    申请日：2007-04-09

    申请人： Uway Tseng ,  Ching-Yu Chang

    发明人： Uway Tseng ,  Ching-Yu Chang

    IPC分类号： H01L21/76

    CPC分类号： H01L21/76224

    摘要： A shallow trench isolation structure has a trench formed in a substrate, a silicon oxynitride layer conformally formed on the sidewalls and bottom of the trench, and a high density plasma (HDP) oxide layer substantially filling the trench.

    摘要翻译： 浅沟槽隔离结构具有在衬底中形成的沟槽，保形地形成在沟槽的侧壁和底部上的氧氮化硅层和基本上填充沟槽的高密度等离子体（HDP）氧化物层。

    Gate electrode and MOS transistor including gate and method of fabricating the same
    6.
    发明申请
    Gate electrode and MOS transistor including gate and method of fabricating the same 审中-公开
    包括栅极的栅电极和MOS晶体管及其制造方法

    公开(公告)号：US20070102748A1

    公开(公告)日：2007-05-10

    申请号：US11269582

    申请日：2005-11-09

    申请人： Uway Tseng ,  Yao-Hui Huang

    发明人： Uway Tseng ,  Yao-Hui Huang

    IPC分类号： H01L21/336 ,  H01L29/76

    CPC分类号： H01L29/4925 ,  H01L21/28035 ,  H01L29/518 ,  H01L29/6659 ,  H01L29/7833

    摘要： A gate electrode. The gate electrode includes a substrate, a gate dielectric layer formed thereon, and a gate conductive layer comprising a stack of polysilicon grains formed on the gate dielectric layer, wherein the average size of the polysilicon grains decreases gradually in a direction away from the substrate. The invention also provides a metal oxide semiconductor (MOS) transistor including the gate and a method of fabricating the MOS transistor.

    摘要翻译： 栅电极。 栅极电极包括基板，形成在其上的栅极电介质层和栅极导电层，栅极导电层包括形成在栅极介电层上的多晶硅晶粒堆叠，其中多晶硅晶粒的平均尺寸在远离衬底的方向上逐渐减小。 本发明还提供了包括栅极的金属氧化物半导体（MOS）晶体管和制造MOS晶体管的方法。

    Dual damascene with via liner
    7.
    发明申请
    Dual damascene with via liner 有权
    双镶嵌带通孔衬垫

    公开(公告)号：US20060170106A1

    公开(公告)日：2006-08-03

    申请号：US11048486

    申请日：2005-01-31

    申请人： Uway Tseng ,  Alex Huang ,  Kun-Szu Liu

    发明人： Uway Tseng ,  Alex Huang ,  Kun-Szu Liu

    IPC分类号： H01L23/52 ,  H01L21/4763

    CPC分类号： H01L23/5226 ,  H01L21/76808 ,  H01L21/76831 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2221/1031 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A dual damascene structure with improved profiles and reduced defects and method of forming the same, the method including forming a first dielectric over a conductive area; forming a first dielectric insulator over the first dielectric; forming a first opening in the first dielectric insulator; lining the opening with a second dielectric; forming a second dielectric insulator over the first dielectric insulator; forming a second opening in the second dielectric insulator overlying and communicating with the first opening; and, filling the first and second openings with a conductive material to electrically communicate with the conductive area.

    摘要翻译： 具有改进的轮廓和减少的缺陷的双镶嵌结构及其形成方法，所述方法包括在导电区域上形成第一电介质; 在所述第一电介质上形成第一电介质绝缘体; 在所述第一介电绝缘体中形成第一开口; 用第二电介质衬里开口; 在所述第一绝缘绝缘体上形成第二电介质绝缘体; 在所述第二绝缘绝缘体中形成第二开口，所述第二开口覆盖并与所述第一开口连通; 并且用导电材料填充第一和第二开口以与导电区域电连通。

    Power devices having reduced on-resistance and methods of their manufacture
    8.
    发明授权
    Power devices having reduced on-resistance and methods of their manufacture 有权
    功率器件具有降低的导通电阻及其制造方法

    公开(公告)号：US08633086B2

    公开(公告)日：2014-01-21

    申请号：US12651322

    申请日：2009-12-31

    申请人： Alex Kalnitsky ,  Hsiao-Chin Tuan ,  Liang-Kai Han ,  Uway Tseng ,  Yuan-Chih Hsieh ,  Hung-Hua Lin

    发明人： Alex Kalnitsky ,  Hsiao-Chin Tuan ,  Liang-Kai Han ,  Uway Tseng ,  Yuan-Chih Hsieh ,  Hung-Hua Lin

    IPC分类号： H01L21/30

    CPC分类号： H01L29/66712 ,  H01L21/78 ,  H01L23/562 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method for forming a support structure for supporting and handling a semiconductor wafer containing vertical FETs formed at the front surface thereof is provided. In one embodiment, a semiconductor wafer is provided having a front surface and a rear surface, wherein the front surface comprises one or more dies separated by dicing lines. The wafer is thinned to a predetermined thickness. A plurality of patterned metal features are formed on a thinned rear surface to provide support for the wafer, wherein each of the plurality of patterned metal features covers substantially one die, leaving the dicing lines substantially uncovered. The wafer is thereafter diced along the dicing lines to separate the one or more dies for later chip packaging.

    摘要翻译： 提供一种形成用于支撑和处理包含形成在其前表面上的垂直FET的半导体晶片的支撑结构的方法。 在一个实施例中，提供具有前表面和后表面的半导体晶片，其中前表面包括由切割线分开的一个或多个裸片。 将晶片减薄至预定厚度。 多个图案化的金属特征形成在薄的后表面上以提供对晶片的支撑，其中多个图案化的金属特征中的每一个基本上覆盖一个管芯，使切割线基本上不被覆盖。 然后，晶片沿着切割线切割，以分离一个或多个模具用于稍后的芯片封装。