公开(公告)号：US09007122B2

公开(公告)日：2015-04-14

申请号：US14202275

申请日：2014-03-10

Applicant: Via Technologies, Inc.

Inventor： James R. Lundberg

IPC: G05F1/10 ,  H03K17/22 ,  G06F1/32 ,  H03K19/00 ,  H03K17/16

CPC classification number: H03K17/22 ,  G06F1/3234 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/3287 ,  G06F1/3296 ,  H03K17/16 ,  H03K19/0008 ,  H03K19/0016 ,  H03K2217/0036 ,  Y02D10/126 ,  Y02D10/152 ,  Y02D10/171 ,  Y02D10/172 ,  Y02D50/20

Abstract: A digital power gating system for performing power gating to reduce a voltage of a gated supply bus to a state retention voltage level that reduces leakage current while retaining a digital state of a functional circuit. The power gating system includes gating devices and a power gating control system. Each gating device has current terminals coupled between a global supply bus and the gated supply bus, and a control terminal controlled by a bit of a digital control value. The power gating control system successively adjusts the digital control value to reduce a voltage of the gated supply bus to the state retention voltage level. Adjustment gain and/or adjustment periods may be changed, such as when the digital control value reaches certain values or when the gated supply reaches certain voltage levels. Various parameters are programmable to adjust for particular configurations or to achieve desired operation.

Abstract translation: 一种用于执行电力门控以将门控电源总线的电压降低到保持功能电路的数字状态的同时降低漏电流的状态保持电压电平的数字电源门控系统。 电源门控系统包括门控设备和电源门控控制系统。 每个选通装置具有耦合在全局电源总线和门控电源总线之间的电流端子，以及由位数位控制值控制的控制端子。 电源门控控制系统连续调整数字控制值，将门控电源总线的电压降至状态保持电压电平。 可以改变调节增益和/或调整周期，例如当数字控制值达到某些值时或当门控电源达到一定的电压电平时。 可以对各种参数进行编程以针对特定配置进行调整或实现​​期望的操作。

公开(公告)号：US20140361828A1

公开(公告)日：2014-12-11

申请号：US14202313

申请日：2014-03-10

Applicant: VIA TECHNOLOGIES, INC.

Inventor： James R. Lundberg

IPC: H03K17/687

CPC classification number: H03K19/0008

Abstract: An integrated circuit including a global supply bus, a gated supply bus, a functional circuit coupled to the gated supply bus, a programmable device that stores a programmed control parameter, and a digital power gating system. The digital power gating system includes gating devices and a power gating control system. Each gating device is coupled between the global and gated supply buses and each has a control terminal. The power gating control system controls a digital control value to control activation of the gating devices. The power gating control system is configured to perform a power gating operation by adjusting the digital control value to control a voltage of the gated supply bus relative to the voltage of the global supply bus. The power gating operation may be adjusted using the programmed control parameter. The programmable device may be a fuse array or a memory programmed with programmed control parameter.

Abstract translation: 包括全局电源总线，门控电源总线，耦合到门控电源总线的功能电路，存储编程控制参数的可编程器件和数字电源门控系统的集成电路。 数字电源门控系统包括门控设备和电源门控控制系统。 每个选通装置耦合在全局和门控供电总线之间，并且每个具有控制终端。 电源门控控制系统控制数字控制值以控制门控设备的激活。 电源门控控制系统被配置为通过调整数字控制值来执行电力门控操作，以控制门控电源总线相对于全局电源总线的电压的电压。 电源门控操作可以使用编程的控制参数进行调整。 可编程器件可以是保险丝阵列或用编程控制参数编程的存储器。

公开(公告)号：US08886855B2

公开(公告)日：2014-11-11

申请号：US13747140

申请日：2013-01-22

Applicant: VIA Technologies, Inc.

Inventor： Vanessa S. Canac ,  James R. Lundberg

IPC: G06F13/00 ,  G06F17/30 ,  G06F13/42

CPC classification number: G06F17/30581 ,  G06F13/4217

Abstract: An apparatus that compensates for misalignment on a synchronous data bus. The apparatus includes a replica distribution network, a bit lag control element, and a synchronous lag receiver. The replica distribution network receives a first signal, and generates a second signal, where the replica distribution network comprises replicated propagation characteristics of a radial distribution network for a strobe. The bit lag control element is configured to measure a propagation time beginning with assertion of the first signal and ending with assertion of the second signal, and is configured to generate a value on a lag bus that indicates the propagation time. The synchronous lag receiver is coupled to the bit lag control element, and is configured to receive a first one of a plurality of radially distributed strobes and a data bit, and is configured to delay registering of the data bit by the propagation time.

Abstract translation: 补偿同步数据总线上的未对准的装置。 该装置包括复制分发网络，位延迟控制元件和同步延迟接收器。 复制分发网络接收第一信号，并且生成第二信号，其中复制分发网络包括用于选通的径向分布网络的复制传播特性。 比特滞后控制元件被配置为测量从第一信号的断言开始并以第二信号的断言结束的传播时间，并且被配置为在指示传播时间的滞后总线上生成值。 同步延迟接收器耦合到位延迟控制元件，并且被配置为接收多个径向分布的选通信号和数据位中的第一个，并被配置为延迟数据位的登记传播时间。

公开(公告)号：US09953002B2

公开(公告)日：2018-04-24

申请号：US15389528

申请日：2016-12-23

Applicant: VIA TECHNOLOGIES, INC.

Inventor： Vanessa Canac ,  James R. Lundberg

IPC: G06F1/12 ,  G06F13/42 ,  G11C8/18 ,  G11C7/10

CPC classification number: G06F13/4243 ,  G06F1/12 ,  G06F13/4217 ,  G11C7/1072 ,  G11C8/18

Abstract: An apparatus is provided that compensates for misalignment on a synchronous data bus. The apparatus includes a replica radial distribution element, a bit lag control element, and a synchronous lag receiver. The replica radial distribution element is configured to receive a lag pulse signal, and is configured to generate a replicated strobe signal, where the replica radial distribution network comprises replicated propagation path lengths, loads, and buffering of a radial distribution network for a strobe. The bit lag control element is configured to measure the time between assertion of the lag pulse signal and assertion of the replicated strobe signal when an update signal is asserted, and is configured to generate a first value on a lag bus that indicates the time. The bit lag control element has delay lock control that is configured to select one of a plurality of successively delayed versions of the lag pulse signal that coincides with the assertion the replicated strobe signal, and is configured to generate a second value on a lag select bus that indicates the propagation time, where the delay lock control selects the one of a plurality of successively delayed versions of the lag pulse signal by incrementing and decrementing bus states of select inputs on a mux, and where the plurality of successively delayed versions comprises inputs to the mux. The synchronous lag receiver is coupled to the bit lag control element, and is configured to receive a first one of a plurality of radially distributed strobes and a data bit, and is configured to delay registering of the data bit by the time.

公开(公告)号：US09319035B2

公开(公告)日：2016-04-19

申请号：US13747187

申请日：2013-01-22

Applicant: VIA Technologies, Inc.

Inventor： Vanessa S. Canac ,  James R. Lundberg

IPC: G06F3/00 ,  G06F5/00 ,  G06F13/42 ,  H03K5/06

CPC classification number: H03K5/06

Abstract: An apparatus having a bit lag control element that measures a propagation time beginning with assertion of a first signal and ending with assertion of a second signal, and that generates a first value indicating an adjusted propagation time. The control element includes delay lock control, adjust logic, and a gray encoder. The delay lock control selects one of a plurality of successively delayed versions of the first signal that coincides with the assertion the second signal, and generates a second value on a lag select bus that indicates the propagation time. The adjust logic is coupled to a circuit and to the lag select bus, and adjusts the second value by an amount prescribed by the circuit to yield a third value that is output to an adjusted lag bus. The gray encoder gray encodes the third value to generate the first value on the lag bus.

Abstract translation: 一种具有位延迟控制元件的装置，其测量从第一信号的断言开始并以第二信号的断言结束的传播时间，并且生成指示经调整的传播时间的第一值。 控制元件包括延迟锁定控制，调整逻辑和灰度编码器。 延迟锁定控制选择与断言第二信号一致的第一信号的多个连续延迟版本中的一个，并在指示传播时间的延迟选择总线上产生第二值。 调整逻辑耦合到电路和滞后选择总线，并且通过电路规定的量来调整第二值，以产生输出到经调整的滞后总线的第三值。 灰色编码器灰度编码第三个值，以产生滞后总线上的第一个值。

公开(公告)号：US09000834B2

公开(公告)日：2015-04-07

申请号：US14202288

申请日：2014-03-10

Applicant: Via Technologies, Inc.

Inventor： James R. Lundberg

IPC: H03K3/01 ,  H03K3/012

CPC classification number: H03K3/012 ,  G06F1/26 ,  G06F1/3243 ,  H03K19/0008 ,  Y02D10/152

Abstract: A system which may be implemented on an integrated circuit including a global supply bus, a gated supply bus, a functional circuit receiving voltage from the gated supply bus, and a digital power gating system. The digital power gating system includes gating devices, a power gating control system, and a global control adjuster. The gating devices are coupled between the global and gated supply buses and are controlled by a digital control value. The power gating control system performs power gating by successively adjusting the digital control value to reduce a voltage of the gated supply bus to a state retention voltage level. The global control adjuster performs a global adjustment of the digital control value to increase the voltage of the gated supply bus to prevent it from falling below the state retention voltage level in response to an impending change of a voltage of the global supply bus.

Abstract translation: 可以在包括全局电源总线，门控电源总线，从门控电源总线接收电压的功能电路以及数字电源门控系统的集成电路上实现的系统。 数字电源门控系统包括门控设备，电源门控控制系统和全局控制调节器。 门控设备耦合在全局和门控供电总线之间，并由数字控制值控制。 电源门控控制系统通过连续调整数字控制值来执行电源门控，以将门控电源总线的电压降低到状态保持电压电平。 全局控制调节器执行数字控制值的全局调整，以增加门控电源总线的电压，以防止其响应于全局电源总线的电压即将发生变化而降低到状态保持电压电平以下。

公开(公告)号：US08963627B2

公开(公告)日：2015-02-24

申请号：US14202298

申请日：2014-03-10

Applicant: Via Technologies, Inc.

Inventor： James R. Lundberg

IPC: G05F1/10 ,  H03K17/22 ,  H03K17/16

CPC classification number: H03K17/22 ,  G06F1/3287 ,  G06F1/3296 ,  H03K17/16 ,  H03K19/0016 ,  H03K2217/0036 ,  Y02D10/171 ,  Y02D10/172

Abstract: An integrated circuit including a global supply bus, a gated supply bus, and a digital power gating system with controlled resume. The digital power gating system includes gating devices and a power gating control system. Each gating device has a pair of current terminals coupled between the global supply bus and the gated supply bus and each has a control terminal. The power gating control system controls a digital control value which controls activation of the gating devices. The power gating control system is configured to successively adjust the digital control value to increase a voltage of the gated supply bus from a reduced voltage level to a normal operating voltage level in response to a resume indication. The reduced voltage level may be a state retention level or full power gating. Successive adjustment may be with constant or adjusted gain using a constant clock or a dynamically adjusted clock.

Abstract translation: 一种集成电路，包括全局电源总线，门控电源总线和具有可控恢复功能的数字电源门控系统。 数字电源门控系统包括门控设备和电源门控控制系统。 每个选通装置具有耦合在全局电源总线和门控电源总线之间的一对电流端子，并且每个具有控制端子。 电源门控控制系统控制控制门控设备激活的数字控制值。 功率选通控制系统被配置为响应于恢复指示，连续地调整数字控制值以将门控电源总线的电压从降低的电压电平增加到正常工作电压电平。 降低的电压电平可以是状态保持电平或全功率门控。 使用恒定时钟或动态调整的时钟可以连续调整恒定或调整的增益。

公开(公告)号：US20140361820A1

公开(公告)日：2014-12-11

申请号：US14202298

申请日：2014-03-10

Applicant: VIA TECHNOLOGIES, INC.

Inventor： James R. Lundberg

IPC: H03K17/22 ,  H03K17/16

CPC classification number: H03K17/22 ,  G06F1/3287 ,  G06F1/3296 ,  H03K17/16 ,  H03K19/0016 ,  H03K2217/0036 ,  Y02D10/171 ,  Y02D10/172

Abstract: An integrated circuit including a global supply bus, a gated supply bus, and a digital power gating system with controlled resume. The digital power gating system includes gating devices and a power gating control system. Each gating device has a pair of current terminals coupled between the global supply bus and the gated supply bus and each has a control terminal. The power gating control system controls a digital control value which controls activation of the gating devices. The power gating control system is configured to successively adjust the digital control value to increase a voltage of the gated supply bus from a reduced voltage level to a normal operating voltage level in response to a resume indication. The reduced voltage level may be a state retention level or full power gating. Successive adjustment may be with constant or adjusted gain using a constant clock or a dynamically adjusted clock.

Abstract translation: 一种集成电路，包括全局电源总线，门控电源总线和具有可控恢复功能的数字电源门控系统。 数字电源门控系统包括门控设备和电源门控控制系统。 每个选通装置具有耦合在全局电源总线和门控电源总线之间的一对电流端子，并且每个具有控制端子。 电源门控控制系统控制控制门控设备激活的数字控制值。 功率选通控制系统被配置为响应于恢复指示，连续地调整数字控制值以将门控电源总线的电压从降低的电压电平增加到正常工作电压电平。 降低的电压电平可以是状态保持电平或全功率门控。 使用恒定时钟或动态调整的时钟可以连续调整恒定或调整的增益。

公开(公告)号：US20140208148A1

公开(公告)日：2014-07-24

申请号：US13757480

申请日：2013-02-01

Applicant: VIA TECHNOLOGIES, INC.

Inventor： Vanessa S. Canac ,  James R. Lundberg

IPC: G06F1/12

CPC classification number: G06F13/4243 ,  G06F1/12 ,  G06F13/4217 ,  G11C7/1072 ,  G11C8/18

Abstract: An apparatus including a Joint Test Action Group (JTAG) interface and a bit lag control element. The JTAG interface receives information that indicates an amount to adjust a propagation time. The bit lag control element measures the propagation time beginning with assertion of a first signal and ending with assertion of a second signal, and generates a value indicating an adjusted propagation time. The bit lag control element includes delay lock control, adjust logic, and a gray encoder. The delay lock control selects one of a plurality of successively delayed versions of the first signal that coincides with the assertion the second signal, and generates a second value indicating the propagation time. The adjust logic adjusts the second value by the amount prescribed by the JTAG interface to yield a third value. The gray encoder gray encodes the third value to generate the value on the lag bus.

Abstract translation: 一种包括联合测试动作组（JTAG）接口和位滞后控制元件的装置。 JTAG接口接收指示调整传播时间的量的信息。 位延迟控制元件测量从第一信号的断言开始并以第二信号的断言结束的传播时间，并产生指示经调整的传播时间的值。 位延迟控制元件包括延迟锁定控制，调整逻辑和灰度编码器。 延迟锁定控制选择与断言第二信号一致的第一信号的多个连续延迟版本中的一个，并且生成指示传播时间的第二值。 调整逻辑将第二个值调整为由JTAG接口规定的量以产生第三个值。 灰色编码器灰度编码第三个值，以产生滞后总线上的值。

公开(公告)号：US20140204691A1

公开(公告)日：2014-07-24

申请号：US13747187

申请日：2013-01-22

Applicant: VIA TECHNOLOGIES, INC.

Inventor： Vanessa S. Canac ,  James R. Lundberg

IPC: H03K5/159

CPC classification number: H03K5/06

Abstract: An apparatus having a bit lag control element that measures a propagation time beginning with assertion of a first signal and ending with assertion of a second signal, and that generates a first value indicating an adjusted propagation time. The control element includes delay lock control, adjust logic, and a gray encoder. The delay lock control selects one of a plurality of successively delayed versions of the first signal that coincides with the assertion the second signal, and generates a second value on a lag select bus that indicates the propagation time. The adjust logic is coupled to a circuit and to the lag select bus, and adjusts the second value by an amount prescribed by the circuit to yield a third value that is output to an adjusted lag bus. The gray encoder gray encodes the third value to generate the first value on the lag bus.

Abstract translation: 一种具有位延迟控制元件的装置，其测量从第一信号的断言开始并以第二信号的断言结束的传播时间，并且生成指示经调整的传播时间的第一值。 控制元件包括延迟锁定控制，调整逻辑和灰度编码器。 延迟锁定控制选择与断言第二信号一致的第一信号的多个连续延迟版本中的一个，并在指示传播时间的延迟选择总线上产生第二值。 调整逻辑耦合到电路和滞后选择总线，并且通过电路规定的量来调整第二值，以产生输出到经调整的滞后总线的第三值。 灰色编码器灰度编码第三个值，以产生滞后总线上的第一个值。