公开(公告)号：US20180173539A1

公开(公告)日：2018-06-21

申请号：US15387332

申请日：2016-12-21

Applicant: VMware, Inc.

Inventor： Andrei Warkentin ,  Cyrien Laplace ,  Alexander Fainkichen ,  Ye Li ,  Regis Duchesne

IPC: G06F9/44 ,  G06F12/1009

CPC classification number: G06F12/1009 ,  G06F9/4401 ,  G06F12/109 ,  G06F12/1441 ,  G06F2212/1008 ,  G06F2212/657

Abstract: Examples construct a bootloader address space using a page fault exception. A bootloader executing in machine address (MA) space determines the MA at which the bootloader has been loaded into memory. The bootloader calculates a difference between an expected virtual address (VA) and the loaded MA. The bootloader defines a page table mapping the bootloader MA to an expected VA, and sets an exception handling vector to point to the expected VA. When a memory management unit (MMU) utilizing the defined page table for address translation is enabled, a page fault exception occurs. The page fault exception handling resumes execution of the bootloader at the expected VA via an exception handling vector pointing thereto.

公开(公告)号：US09952895B2

公开(公告)日：2018-04-24

申请号：US14876831

申请日：2015-10-07

Applicant: VMWARE, INC.

Inventor： Andrei Warkentin ,  Irfan Ulla Khan ,  Cyprien Laplace ,  Harvey Tuch ,  Alexander Fainkichen

IPC: G06F13/24 ,  G06F13/00 ,  G06F9/48 ,  G06F13/26

CPC classification number: G06F9/4818 ,  G06F13/26

Abstract: A method is provided for handling interrupts in a processor, the interrupts including regular interrupts having a range of priorities and a pseudo non-maskable interrupt (PNMI) that is of a higher priority than any of the regular interrupts. The method includes the steps of obtaining an interrupt vector corresponding to a received interrupt, and if the received interrupt is a regular interrupt, enabling interrupts in the processor so that a PNMI can be received while handling the regular interrupt, executing a regular interrupt handler using the interrupt vector, and disabling interrupts in the processor. On the other hand, if the received interrupt is a PNMI, a PNMI interrupt handler is executed using the interrupt vector as an input thereto.

公开(公告)号：US09952887B2

公开(公告)日：2018-04-24

申请号：US14312249

申请日：2014-06-23

Applicant: VMware, Inc.

Inventor： Andrei Warkentin ,  Harvey Tuch

IPC: G06F7/04 ,  G06F9/455 ,  G06F21/74

CPC classification number: G06F9/45516 ,  G06F9/45533 ,  G06F21/74

Abstract: A secure mode of a computer system is used to provide simulated devices. In operation, if an instruction executing in a non-secure mode accesses a simulated device, then a resulting exception is forwarded to a secure monitor executing in the secure mode. Based on the address accessed by the instruction, the secure monitor identifies the device and simulates the instruction. The secure monitor executes independently of other applications included in the computer system, and does not rely on any hardware virtualization capabilities of the computer system.

公开(公告)号：US12197939B2

公开(公告)日：2025-01-14

申请号：US17704052

申请日：2022-03-25

Applicant: VMWARE, INC.

Inventor： Andrei Warkentin ,  Aravinda Haryadi ,  Lingyuan He ,  Suman Boro ,  Karthik Ramachandra ,  Anjaneya Prasad Gondi ,  Renaud Benjamin Voltz

IPC: G06F9/455 ,  G06F8/61 ,  G06F9/4401 ,  H04L67/1097

Abstract: Disclosed are various examples of provisioning a data processing unit (DPU) management operating system (OS). A management hypervisor installer executed on a host device launches or causes a server component to provide a management operating system (OS) installer image at a particular URI accessible over a network internal to the host device. A baseboard management controller (BMC) transfers the DPU management OS installer image to the DPU device. A volatile memory based virtual disk is created using the DPU management OS installer image. The DPU device is booted to a DPU management OS installer on the volatile memory based virtual disk. The DPU management OS installer installs a DPU management operating system to a nonvolatile memory of the DPU device on reboot of the DPU device.

公开(公告)号：US20240028547A1

公开(公告)日：2024-01-25

申请号：US17869272

申请日：2022-07-20

Applicant: VMware, Inc.

Inventor： Andrei Warkentin

IPC: G06F13/42

CPC classification number: G06F13/4221 ,  G06F2213/0026

Abstract: Disclosed are various approaches for exposing peripheral component interconnect express (PCIe) configuration space implementations as Enhanced Configuration Access Mechanism (ECAM)-compatible. In some examples, a bridge device is identified on a segment corresponding to a root complex of a computing device. An endpoint device is connected to a bus downstream from the bridge device. A synthetic segment identifier is assigned to the bus once the endpoint device is identified as connected to the bus. Synthetic address data is generated for the endpoint device. The synthetic address data includes the synthetic segment identifier for the bus and sets a bus identifier of the bus to zero regardless of a hierarchical position of the bus in a standard peripheral component interconnect express (PCIe) bus hierarchy.

公开(公告)号：US20230350815A1

公开(公告)日：2023-11-02

申请号：US18340120

申请日：2023-06-23

Applicant: VMware, Inc.

Inventor： Srihari Venkatesan ,  Sunil Kotian ,  Andrei Warkentin ,  Kalaiselvi Sengottuvel

IPC: G06F12/14 ,  G06F12/109 ,  G06F13/42 ,  G06F9/455 ,  G06F12/02

CPC classification number: G06F12/145 ,  G06F12/1433 ,  G06F12/109 ,  G06F13/4221 ,  G06F9/45558 ,  G06F12/0238 ,  G06F2009/45587 ,  G06F2009/45583

Abstract: Disclosed are various embodiments for various approaches for implementing trust domains to provide boundaries between PCIe devices connected to the same PCIe switch. A first trust identifier can be assigned to a first virtual machine hosted by the computing device. The first trust identifier can also be assigned to a first PCIe device assigned to the first virtual machine. Later, it can be determined that a second PCIe device connected to the PCIe switch is assigned a second trust identifier assigned to a second virtual machine. An Address Control Services (ACS) direct translated bit for peer-to-peer memory requests in the PCIe switch can be disabled in response to a determination that the second PCIe device is associated with the second trust identifier assigned to the second virtual machine.

公开(公告)号：US20230325223A1

公开(公告)日：2023-10-12

申请号：US17716083

申请日：2022-04-08

Applicant: VMware, Inc.

Inventor： Andrei Warkentin ,  Sunil Kotian

IPC: G06F9/455 ,  G06F9/4401

CPC classification number: G06F9/45558 ,  G06F9/4401 ,  G06F2009/45583

Abstract: Disclosed are various examples of loading management hypervisors from user space. In some examples, a host device executes a first stage bootloader of a management hypervisor from within a host operating system. The first stage bootloader loads management hypervisor data and handoff instructions into a memory of the host device, and invokes a kernel execute call of the host operating system. The handoff instructions invoke a second stage bootloader that configures and launches the management hypervisor using the management hypervisor data.

公开(公告)号：US20230229307A1

公开(公告)日：2023-07-20

申请号：US17578680

申请日：2022-01-19

Applicant: VMware, Inc.

Inventor： Andrei Warkentin ,  Sunil Kotian

IPC: G06F3/06 ,  G06F9/455

CPC classification number: G06F3/0608 ,  G06F9/45558 ,  G06F3/0655 ,  G06F3/0679 ,  G06F2009/45583

Abstract: Disclosed are various examples of providing efficient bit compression for direct mapping of physical memory addresses. In some examples, a hypervisor operating system component generates a mask of used address space bits indicated by memory map entries for a computing device. A longest range of unused address space bits is identified using the mask. The memory map entries are transformed to omit the longest range of unused address space bits.

公开(公告)号：US11550609B2

公开(公告)日：2023-01-10

申请号：US16744356

申请日：2020-01-16

Applicant: VMware, Inc.

Inventor： Andrei Warkentin ,  Cyprien Laplace ,  Regis Duchesne ,  Alexander Fainkichen ,  Shruthi Muralidhara Hiriyuru ,  Ye Li

IPC: G06F9/455

Abstract: An example method of interfacing with a hypervisor in a computing system is described, which includes a processor having at least three hierarchical privilege levels including a third privilege level more privileged than a second privilege level, the second privilege level more privileged than a first privilege level. The method includes: identifying an input/output (I/O) space instruction, not supported by the processor, to be performed for backdoor communication between the hypervisor and guest software executing in a virtual machine (VM) managed by the hypervisor, the hypervisor executing at the third privilege level; writing one or more parameters to one or more registers of the processor that are mapped to one or more unsupported registers used by the I/O space instruction; writing a value indicative of the I/O space instruction to a designated register of the processor; executing an instruction, by the guest software executing at the first or second privilege level, which is trapped to the third privilege level.

公开(公告)号：US11422840B2

公开(公告)日：2022-08-23

申请号：US14982837

申请日：2015-12-29

Applicant: VMware, Inc.

Inventor： Andrei Warkentin ,  Harvey Tuch ,  Cyprien Laplace ,  Alexander Fainkichen

IPC: G06F9/455

Abstract: In an example, a computer system includes a hardware platform and a hypervisor executing on the hardware platform. The hypervisor includes a kernel and a plurality of user-space instances within a user-space above the kernel. Each user-space instance is isolated from each other user-space instance through namespaces. Each user-space instance includes resources confined by hierarchical resource groups. The computer system includes a plurality of virtual hypervisors, where each virtual hypervisor executes in a respective user-space instance of the plurality of user-space instances.