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    Vertical heterostructure field effect transistor and associated method
    11.
    发明授权
    Vertical heterostructure field effect transistor and associated method 有权
    垂直异质结场场效应晶体管及相关方法

    公开(公告)号：US07521732B2

    公开(公告)日：2009-04-21

    申请号：US11283451

    申请日：2005-11-18

    申请人： Kevin Sean Matocha ,  Vinayak Tilak

    发明人： Kevin Sean Matocha ,  Vinayak Tilak

    IPC分类号： H01L29/20

    CPC分类号： H01L29/7787 ,  H01L29/045 ,  H01L29/2003 ,  H01L29/42316 ,  H01L29/4236 ,  H01L29/7788 ,  H01L29/7789

    摘要： A vertical heterostructure field effect transistor including a first layer having a first material, and the first material having a hexagonal crystal lattice structure defining a first bandgap and one or more non-polar planes is provided. The transistor further includes a second layer that is adjacent to the first layer having a second material. Further, the second layer has a first surface and a second surface, and a portion of the second layer first surface is coupled to the surface of the first layer to form a two dimensional charge gas and to define a first region. The second material may have a second bandgap that is different than the first bandgap. Furthermore, the transistor may include a conductive layer that is disposed in the trench and is interposed between the first region and a second region that is not in electrical communication with the first region if no electrical potential is applied to the conductive layer, and an electrical potential applied to the conductive layer allows electrical communication from the first region to the second region.

    摘要翻译： 提供了一种垂直异质结场效应晶体管，其包括具有第一材料的第一层，并且提供了具有限定第一带隙和一个或多个非极性平面的六方晶格结构的第一材料。 所述晶体管还包括与所述第一层相邻的第二层，所述第二层具有第二材料。 此外，第二层具有第一表面和第二表面，并且第二层第一表面的一部分耦合到第一层的表面以形成二维充电气体并限定第一区域。 第二材料可以具有与第一带隙不同的第二带隙。 此外，晶体管可以包括设置在沟槽中并且如果没有电位施加到导电层的第一区域和不与第一区域电连通的第二区域的导电层， 施加到导电层的电位允许从第一区域到第二区域的电连通。

    SiC SUBSTRATES, SEMICONDUCTOR DEVICES BASED UPON THE SAME AND METHODS FOR THEIR MANUFACTURE
    13.
    发明申请
    SiC SUBSTRATES, SEMICONDUCTOR DEVICES BASED UPON THE SAME AND METHODS FOR THEIR MANUFACTURE 审中-公开
    SiC基板，基于其的半导体器件及其制造方法

    公开(公告)号：US20100123140A1

    公开(公告)日：2010-05-20

    申请号：US12275067

    申请日：2008-11-20

    申请人： Victor Lienkong Lou ,  Kevin Sean Matocha ,  Aveek Chatterjee ,  Vinayak Tilak ,  Stephen Arthur ,  Zachary Stum

    发明人： Victor Lienkong Lou ,  Kevin Sean Matocha ,  Aveek Chatterjee ,  Vinayak Tilak ,  Stephen Arthur ,  Zachary Stum

    IPC分类号： H01L21/30 ,  H01L29/24

    CPC分类号： H01L21/049

    摘要： The present invention generally relates to a method for improving inversion layer mobility and providing low defect density in a semiconductor device based upon a silicon carbide (SiC) substrate. More specifically, the present invention provides a method for the manufacture of a semiconductor device based upon a silicon carbide substrate and comprising an oxide layer comprising incorporating at least one additive into the atomic structure of the oxide layer. Semiconductor devices, such as MOSFETS, based upon a substrate treated according to the present method are expected to have inversion layer mobilities of at least about 60 cm2/Vs.

    摘要翻译： 本发明一般涉及一种在基于碳化硅（SiC）衬底的半导体器件中提高反层迁移率和提供低缺陷密度的方法。 更具体地说，本发明提供一种制造基于碳化硅衬底的半导体器件的方法，该方法包括将至少一种添加剂结合到氧化物层的原子结构中的氧化物层。 预期基于根据本方法处理的衬底的诸如MOSFET的半导体器件具有至少约60cm 2 / Vs的反转层迁移率。

    Method for fabricating silicon carbide vertical MOSFET devices
    14.
    发明授权
    Method for fabricating silicon carbide vertical MOSFET devices 有权
    制造碳化硅垂直MOSFET器件的方法

    公开(公告)号：US07595241B2

    公开(公告)日：2009-09-29

    申请号：US11466488

    申请日：2006-08-23

    申请人： Kevin Sean Matocha ,  Jody Alan Fronheiser ,  Larry Burton Rowland ,  Jesse Berkley Tucker ,  Stephen Daley Arthur ,  Zachary Matthew Stum

    发明人： Kevin Sean Matocha ,  Jody Alan Fronheiser ,  Larry Burton Rowland ,  Jesse Berkley Tucker ,  Stephen Daley Arthur ,  Zachary Matthew Stum

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7802 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/41766 ,  H01L29/66068

    摘要： A method of forming a vertical MOSFET device includes forming a trench within a drift layer substrate, the drift layer comprising a first polarity type, the trench generally defining a well region of a second polarity type opposite the first polarity type. An ohmic contact layer is formed within a bottom surface of the trench, the ohmic contact layer comprising a material of the second polarity type. A layer of the second polarity type is epitaxially grown over the drift layer, sidewall surfaces of the trench, and the ohmic contact layer. A layer of the first polarity type is epitaxially grown over the epitaxially grown layer of the second polarity type so as to refill the trench, and the epitaxially grown layers of the first and second polarity type are planarized so as to expose an upper surface of the drift layer substrate.

    摘要翻译： 形成垂直MOSFET器件的方法包括在漂移层衬底内形成沟槽，漂移层包括第一极性类型，沟槽通常限定与第一极性类型相反的第二极性类型的阱区。 欧姆接触层形成在沟槽的底表面内，欧姆接触层包括第二极性类型的材料。 在漂移层，沟槽的侧壁表面和欧姆接触层上外延生长第二极性类型的层。 第一极性类型的层在第二极性类型的外延生长层上外延生长，以便重新填充沟槽，并且将第一和第二极性类型的外延生长层平坦化，以暴露出第二极性类型的上表面 漂移层基板。

    SiC MOSFETs and self-aligned fabrication methods thereof
    15.
    发明申请
    SiC MOSFETs and self-aligned fabrication methods thereof 审中-公开
    SiC MOSFET及其自对准制造方法

    公开(公告)号：US20080108190A1

    公开(公告)日：2008-05-08

    申请号：US11593317

    申请日：2006-11-06

    申请人： Kevin Sean Matocha

    发明人： Kevin Sean Matocha

    IPC分类号： H01L21/8234

    CPC分类号： H01L29/66068 ,  H01L21/0465 ,  H01L29/1608 ,  H01L29/7827

    摘要： The present invention provides a method of fabricating a metal oxide semiconductor field effect transistor. The method includes the steps of forming a source region on a silicon carbide layer and annealing the source region. A gate oxide layer is formed on the source region and the silicon carbide layer. The method further includes providing a gate electrode on the gate oxide layer and disposing a dielectric layer on the gate electrode and the gate oxide layer. The method further includes etching a portion of the dielectric layer and a portion of the gate oxide layer to form sidewalls on the gate electrode. A metal layer is disposed on the gate electrode, the sidewalls and the source region. The method further includes forming a gate contact and a source contact by subjecting the metal layer to a temperature of at least about 800 degrees Celsius. The gate contact and the source contact comprise a metal silicide. The distance between the gate contact and the source contact is less than about 0.6 micrometers. A vertical SiC MOSFET is also provided.

    摘要翻译： 本发明提供一种制造金属氧化物半导体场效应晶体管的方法。 该方法包括以下步骤：在碳化硅层上形成源极区域并退火源极区域。 在源区和碳化硅层上形成栅氧化层。 该方法还包括在栅极氧化物层上设置栅电极，并在栅电极和栅极氧化物层上设置电介质层。 该方法还包括蚀刻介电层的一部分和栅极氧化物层的一部分以在栅电极上形成侧壁。 金属层设置在栅电极，侧壁和源极区上。 该方法还包括通过使金属层经受至少约800摄氏度的温度来形成栅极接触和源极接触。 栅极接触和源极接触包括金属硅化物。 栅极接触点和源极接触点之间的距离小于约0.6微米。 还提供了一个垂直的SiC MOSFET。

    SiC MOSFETs and self-aligned fabrication methods thereof
    18.
    发明授权
    SiC MOSFETs and self-aligned fabrication methods thereof 有权
    SiC MOSFET及其自对准制造方法

    公开(公告)号：US08377812B2

    公开(公告)日：2013-02-19

    申请号：US12483469

    申请日：2009-06-12

    申请人： Kevin Sean Matocha ,  Gregory Keith Dudoff ,  William Gregg Hawkins ,  Zachary Matthew Stum ,  Stephen Daley Arthur ,  Dale Marius Brown

    发明人： Kevin Sean Matocha ,  Gregory Keith Dudoff ,  William Gregg Hawkins ,  Zachary Matthew Stum ,  Stephen Daley Arthur ,  Dale Marius Brown

    IPC分类号： H01L21/28

    CPC分类号： H01L29/4975 ,  H01L21/0465 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7827 ,  H01L29/872

    摘要： The present invention provides a method of fabricating a metal oxide semiconductor field effect transistor. The method includes the steps of forming a source region on a silicon carbide layer and annealing the source region. A gate oxide layer is formed on the source region and the silicon carbide layer. The method further includes providing a gate electrode on the gate oxide layer and disposing a dielectric layer on the gate electrode and the gate oxide layer. The method further includes etching a portion of the dielectric layer and a portion of the gate oxide layer to form sidewalls on the gate electrode. A metal layer is disposed on the gate electrode, the sidewalls and the source region. The method further includes forming a gate contact and a source contact by subjecting the metal layer to a temperature of at least about 800° C. The gate contact and the source contact comprise a metal silicide. The distance between the gate contact and the source contact is less than about 0.6 μm. A vertical SiC MOSFET is also provided.

    摘要翻译： 本发明提供一种制造金属氧化物半导体场效应晶体管的方法。 该方法包括以下步骤：在碳化硅层上形成源极区域并退火源极区域。 在源区和碳化硅层上形成栅氧化层。 该方法还包括在栅极氧化物层上设置栅电极，并在栅电极和栅极氧化物层上设置电介质层。 该方法还包括蚀刻介电层的一部分和栅极氧化物层的一部分以在栅电极上形成侧壁。 金属层设置在栅电极，侧壁和源极区上。 该方法还包括通过使金属层经受至少约800℃的温度来形成栅极接触和源极接触。栅极接触和源极接触包括金属硅化物。 栅极接触点和源极接触点之间的距离小于约0.6μm。 还提供了一个垂直的SiC MOSFET。