公开(公告)号：US10367089B2

公开(公告)日：2019-07-30

申请号：US13431596

申请日：2012-03-27

申请人： Stephen Daley Arthur ,  Joseph Darryl Michael ,  Tammy Lynn Johnson ,  David Alan Lilienfeld ,  Kevin Sean Matocha ,  Jody Alan Fronheiser ,  William Gregg Hawkins

发明人： Stephen Daley Arthur ,  Joseph Darryl Michael ,  Tammy Lynn Johnson ,  David Alan Lilienfeld ,  Kevin Sean Matocha ,  Jody Alan Fronheiser ,  William Gregg Hawkins

IPC分类号： H01L21/04 ,  H01L29/16 ,  H01L29/45 ,  H01L29/49 ,  H01L29/78 ,  H01L29/739 ,  H01L29/745

摘要： According to one embodiment, a semiconductor device, having a semiconductor substrate comprising silicon carbide with a gate electrode disposed on a portion of the substrate on a first surface with, a drain electrode disposed on a second surface of the substrate. There is a dielectric layer disposed on the gate electrode and a remedial layer disposed about the dielectric layer, wherein the remedial layer is configured to mitigate negative bias temperature instability maintaining a change in threshold voltage of less than about 1 volt. A source electrode is disposed on the remedial layer, wherein the source electrode is electrically coupled to a contact region of the semiconductor substrate.

公开(公告)号：US20130075756A1

公开(公告)日：2013-03-28

申请号：US13431596

申请日：2012-03-27

申请人： Stephen Daley Arthur ,  Joseph Darryl Michael ,  Tammy Lynn Johnson ,  David Alan Lilienfeld ,  Kevin Sean Matocha ,  Jody Alan Fronheiser ,  William Gregg Hawkins

发明人： Stephen Daley Arthur ,  Joseph Darryl Michael ,  Tammy Lynn Johnson ,  David Alan Lilienfeld ,  Kevin Sean Matocha ,  Jody Alan Fronheiser ,  William Gregg Hawkins

IPC分类号： H01L29/78

CPC分类号： H01L29/78 ,  H01L21/045 ,  H01L29/1608 ,  H01L29/45 ,  H01L29/4925 ,  H01L29/4933 ,  H01L29/7395 ,  H01L29/7455 ,  H01L29/7802

摘要： According to one embodiment, a semiconductor device, having a semiconductor substrate comprising silicon carbide with a gate electrode disposed on a portion of the substrate on a first surface with, a drain electrode disposed on a second surface of the substrate. There is a dielectric layer disposed on the gate electrode and a remedial layer disposed about the dielectric layer, wherein the remedial layer is configured to mitigate negative bias temperature instability maintaining a change in threshold voltage of less than about 1 volt. A source electrode is disposed on the remedial layer, wherein the source electrode is electrically coupled to a contact region of the semiconductor substrate.

摘要翻译： 根据一个实施例，一种半导体器件，其具有半导体衬底，该半导体衬底包括碳化硅，栅极设置在第一表面上的衬底的一部分上，漏电极设置在衬底的第二表面上。 设置在栅电极上的电介质层和围绕电介质层设置的补救层，其中补救层配置成减轻负偏压温度不稳定性，保持阈值电压的变化小于约1伏。 源电极设置在补救层上，其中源极电耦合到半导体衬底的接触区域。

公开(公告)号：US07595241B2

公开(公告)日：2009-09-29

申请号：US11466488

申请日：2006-08-23

申请人： Kevin Sean Matocha ,  Jody Alan Fronheiser ,  Larry Burton Rowland ,  Jesse Berkley Tucker ,  Stephen Daley Arthur ,  Zachary Matthew Stum

发明人： Kevin Sean Matocha ,  Jody Alan Fronheiser ,  Larry Burton Rowland ,  Jesse Berkley Tucker ,  Stephen Daley Arthur ,  Zachary Matthew Stum

IPC分类号： H01L21/336

CPC分类号： H01L29/7802 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/41766 ,  H01L29/66068

摘要： A method of forming a vertical MOSFET device includes forming a trench within a drift layer substrate, the drift layer comprising a first polarity type, the trench generally defining a well region of a second polarity type opposite the first polarity type. An ohmic contact layer is formed within a bottom surface of the trench, the ohmic contact layer comprising a material of the second polarity type. A layer of the second polarity type is epitaxially grown over the drift layer, sidewall surfaces of the trench, and the ohmic contact layer. A layer of the first polarity type is epitaxially grown over the epitaxially grown layer of the second polarity type so as to refill the trench, and the epitaxially grown layers of the first and second polarity type are planarized so as to expose an upper surface of the drift layer substrate.

摘要翻译： 形成垂直MOSFET器件的方法包括在漂移层衬底内形成沟槽，漂移层包括第一极性类型，沟槽通常限定与第一极性类型相反的第二极性类型的阱区。 欧姆接触层形成在沟槽的底表面内，欧姆接触层包括第二极性类型的材料。 在漂移层，沟槽的侧壁表面和欧姆接触层上外延生长第二极性类型的层。 第一极性类型的层在第二极性类型的外延生长层上外延生长，以便重新填充沟槽，并且将第一和第二极性类型的外延生长层平坦化，以暴露出第二极性类型的上表面 漂移层基板。

公开(公告)号：US20080050876A1

公开(公告)日：2008-02-28

申请号：US11466488

申请日：2006-08-23

申请人： Kevin Sean Matocha ,  Jody Alan Fronheiser ,  Larry Burton Rowland ,  Jesse Berkley Tucker ,  Stephen Daley Arthur ,  Zachary Matthew Stum

发明人： Kevin Sean Matocha ,  Jody Alan Fronheiser ,  Larry Burton Rowland ,  Jesse Berkley Tucker ,  Stephen Daley Arthur ,  Zachary Matthew Stum

IPC分类号： H01L21/336

CPC分类号： H01L29/7802 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/41766 ,  H01L29/66068

摘要： A method of forming a vertical MOSFET device includes forming a trench within a drift layer substrate, the drift layer comprising a first polarity type, the trench generally defining a well region of a second polarity type opposite the first polarity type. An ohmic contact layer is formed within a bottom surface of the trench, the ohmic contact layer comprising a material of the second polarity type. A layer of the second polarity type is epitaxially grown over the drift layer, sidewall surfaces of the trench, and the ohmic contact layer. A layer of the first polarity type is epitaxially grown over the epitaxially grown layer of the second polarity type so as to refill the trench, and the epitaxially grown layers of the first and second polarity type are planarized so as to expose an upper surface of the drift layer substrate.

摘要翻译： 形成垂直MOSFET器件的方法包括在漂移层衬底内形成沟槽，漂移层包括第一极性类型，沟槽通常限定与第一极性类型相反的第二极性类型的阱区。 欧姆接触层形成在沟槽的底表面内，欧姆接触层包括第二极性类型的材料。 在漂移层，沟槽的侧壁表面和欧姆接触层上外延生长第二极性类型的层。 第一极性类型的层在第二极性类型的外延生长层上外延生长，以便重新填充沟槽，并且将第一和第二极性类型的外延生长层平坦化，以暴露出第二极性类型的上表面 漂移层基板。

公开(公告)号：US20090267141A1

公开(公告)日：2009-10-29

申请号：US12498630

申请日：2009-07-07

申请人： Kevin Sean Matocha ,  Jody Alan Fronheiser ,  Larry Burton Rowland ,  Jesse Berkley Tucker ,  Stephen Daley Arthur ,  Zachary Matthew Stum

发明人： Kevin Sean Matocha ,  Jody Alan Fronheiser ,  Larry Burton Rowland ,  Jesse Berkley Tucker ,  Stephen Daley Arthur ,  Zachary Matthew Stum

IPC分类号： H01L29/78 ,  H01L21/22

CPC分类号： H01L29/7802 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/41766 ,  H01L29/66068

摘要： A method of forming a vertical MOSFET device includes forming a trench within a drift layer substrate, the drift layer comprising a first polarity type, the trench generally defining a well region of a second polarity type opposite the first polarity type. An ohmic contact layer is formed within a bottom surface of the trench, the ohmic contact layer comprising a material of the second polarity type. A layer of the second polarity type is epitaxially grown over the drift layer, sidewall surfaces of the trench, and the ohmic contact layer. A layer of the first polarity type is epitaxially grown over the epitaxially grown layer of the second polarity type so as to refill the trench, and the epitaxially grown layers of the first and second polarity type are planarized so as to expose an upper surface of the drift layer substrate.

摘要翻译： 形成垂直MOSFET器件的方法包括在漂移层衬底内形成沟槽，漂移层包括第一极性类型，沟槽通常限定与第一极性类型相反的第二极性类型的阱区。 欧姆接触层形成在沟槽的底表面内，欧姆接触层包括第二极性类型的材料。 在漂移层，沟槽的侧壁表面和欧姆接触层上外延生长第二极性类型的层。 第一极性类型的层在第二极性类型的外延生长层上外延生长，以便重新填充沟槽，并且将第一和第二极性类型的外延生长层平坦化，以暴露出第二极性类型的上表面 漂移层基板。

公开(公告)号：US20090242901A1

公开(公告)日：2009-10-01

申请号：US12483469

申请日：2009-06-12

申请人： Kevin Sean Matocha ,  Gregory Keith Dudoff ,  William Gregg Hawkins ,  Zachary Matthew Stum ,  Stephen Daley Arthur ,  Dale Marius Brown

发明人： Kevin Sean Matocha ,  Gregory Keith Dudoff ,  William Gregg Hawkins ,  Zachary Matthew Stum ,  Stephen Daley Arthur ,  Dale Marius Brown

IPC分类号： H01L29/24 ,  H01L21/285 ,  H01L29/772

CPC分类号： H01L29/4975 ,  H01L21/0465 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7827 ,  H01L29/872

摘要： The present invention provides a method of fabricating a metal oxide semiconductor field effect transistor. The method includes the steps of forming a source region on a silicon carbide layer and annealing the source region. A gate oxide layer is formed on the source region and the silicon carbide layer. The method further includes providing a gate electrode on the gate oxide layer and disposing a dielectric layer on the gate electrode and the gate oxide layer. The method further includes etching a portion of the dielectric layer and a portion of the gate oxide layer to form sidewalls on the gate electrode. A metal layer is disposed on the gate electrode, the sidewalls and the source region. The method further includes forming a gate contact and a source contact by subjecting the metal layer to a temperature of at least about 800° C. The gate contact and the source contact comprise a metal silicide. The distance between the gate contact and the source contact is less than about 0.6 μm. A vertical SiC MOSFET is also provided.

摘要翻译： 本发明提供一种制造金属氧化物半导体场效应晶体管的方法。 该方法包括以下步骤：在碳化硅层上形成源极区域并退火源极区域。 在源区和碳化硅层上形成栅氧化层。 该方法还包括在栅极氧化物层上设置栅电极，并在栅电极和栅极氧化物层上设置电介质层。 该方法还包括蚀刻介电层的一部分和栅极氧化物层的一部分以在栅电极上形成侧壁。 金属层设置在栅电极，侧壁和源极区上。 该方法还包括通过使金属层经受至少约800℃的温度来形成栅极接触和源极接触。栅极接触和源极接触包括金属硅化物。 栅极触点与源极之间的距离小于0.6μm。 还提供了一个垂直的SiC MOSFET。

公开(公告)号：US08377812B2

公开(公告)日：2013-02-19

申请号：US12483469

申请日：2009-06-12

申请人： Kevin Sean Matocha ,  Gregory Keith Dudoff ,  William Gregg Hawkins ,  Zachary Matthew Stum ,  Stephen Daley Arthur ,  Dale Marius Brown

发明人： Kevin Sean Matocha ,  Gregory Keith Dudoff ,  William Gregg Hawkins ,  Zachary Matthew Stum ,  Stephen Daley Arthur ,  Dale Marius Brown

IPC分类号： H01L21/28

CPC分类号： H01L29/4975 ,  H01L21/0465 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7827 ,  H01L29/872

摘要： The present invention provides a method of fabricating a metal oxide semiconductor field effect transistor. The method includes the steps of forming a source region on a silicon carbide layer and annealing the source region. A gate oxide layer is formed on the source region and the silicon carbide layer. The method further includes providing a gate electrode on the gate oxide layer and disposing a dielectric layer on the gate electrode and the gate oxide layer. The method further includes etching a portion of the dielectric layer and a portion of the gate oxide layer to form sidewalls on the gate electrode. A metal layer is disposed on the gate electrode, the sidewalls and the source region. The method further includes forming a gate contact and a source contact by subjecting the metal layer to a temperature of at least about 800° C. The gate contact and the source contact comprise a metal silicide. The distance between the gate contact and the source contact is less than about 0.6 μm. A vertical SiC MOSFET is also provided.

摘要翻译： 本发明提供一种制造金属氧化物半导体场效应晶体管的方法。 该方法包括以下步骤：在碳化硅层上形成源极区域并退火源极区域。 在源区和碳化硅层上形成栅氧化层。 该方法还包括在栅极氧化物层上设置栅电极，并在栅电极和栅极氧化物层上设置电介质层。 该方法还包括蚀刻介电层的一部分和栅极氧化物层的一部分以在栅电极上形成侧壁。 金属层设置在栅电极，侧壁和源极区上。 该方法还包括通过使金属层经受至少约800℃的温度来形成栅极接触和源极接触。栅极接触和源极接触包括金属硅化物。 栅极接触点和源极接触点之间的距离小于约0.6μm。 还提供了一个垂直的SiC MOSFET。

公开(公告)号：US07906427B2

公开(公告)日：2011-03-15

申请号：US12251341

申请日：2008-10-14

申请人： Jody Alan Fronheiser ,  Peter Micah Sandvik ,  Kevin Sean Matocha ,  Vinayak Tilak

发明人： Jody Alan Fronheiser ,  Peter Micah Sandvik ,  Kevin Sean Matocha ,  Vinayak Tilak

IPC分类号： H01L21/4763

CPC分类号： H01L29/66068 ,  H01L22/12 ,  H01L22/26 ,  H01L29/0873 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/6606 ,  H01L29/7813 ,  Y02P80/30

摘要： There is provided a method for dimension profiling of a semiconductor device. The method involves incorporating a feature comprising a detectable element into the device, and thereafter detecting the detectable element to determine a dimension of the feature. This information can be used for the determination of a dimension of buried channels, and also for end-point detection of CMP processes.

摘要翻译： 提供了一种用于半导体器件的尺寸分布的方法。 该方法包括将包括可检测元件的特征结合到该装置中，并且此后检测可检测元件以确定特征的尺寸。 该信息可用于确定掩埋通道的尺寸，也可用于CMP工艺的端点检测。

公开(公告)号：US20100093116A1

公开(公告)日：2010-04-15

申请号：US12251341

申请日：2008-10-14

申请人： Jody Alan Fronheiser ,  Peter Micah Sandvik ,  Kevin Sean Matocha ,  Vinayak Tilak

发明人： Jody Alan Fronheiser ,  Peter Micah Sandvik ,  Kevin Sean Matocha ,  Vinayak Tilak

IPC分类号： H01L21/66

CPC分类号： H01L29/66068 ,  H01L22/12 ,  H01L22/26 ,  H01L29/0873 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/6606 ,  H01L29/7813 ,  Y02P80/30

摘要： There is provided a method for dimension profiling of a semiconductor device. The method involves incorporating a feature comprising a detectable element into the device, and thereafter detecting the detectable element to determine a dimension of the feature. This information can be used for the determination of a dimension of buried channels, and also for end-point detection of CMP processes.

摘要翻译： 提供了一种用于半导体器件的尺寸分布的方法。 该方法包括将包括可检测元件的特征结合到该装置中，并且此后检测可检测元件以确定特征的尺寸。 该信息可用于确定掩埋通道的尺寸，也可用于CMP工艺的端点检测。

公开(公告)号：US07691711B2

公开(公告)日：2010-04-06

申请号：US12023369

申请日：2008-01-31

申请人： Zachary Matthew Stum ,  Kevin Sean Matocha ,  Jody Alan Fronheiser ,  Ljubisa Dragoljub Stevanovic

发明人： Zachary Matthew Stum ,  Kevin Sean Matocha ,  Jody Alan Fronheiser ,  Ljubisa Dragoljub Stevanovic

IPC分类号： H01L21/336

CPC分类号： H01L29/7802 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/66068

摘要： A method of forming a vertical MOSFET device includes forming a first trench within a semiconductor layer of a first polarity, the first trench generally defining a well region of a second polarity opposite the first polarity; growing a first epitaxial well layer of the second polarity over the original semiconductor layer; growing a second epitaxial source contact layer of the first polarity over the well layer; forming a second trench through the source contact layer and at least a portion of the well layer; growing a third epitaxial layer of the second polarity over the source contact layer; and planarizing at least the first and second epitaxial layers so as to expose an upper surface of the original semiconductor layer, wherein a top surface of the third epitaxial layer is substantially coplanar with a top surface of the source contact layer prior to ohmic contact formation.

摘要翻译： 形成垂直MOSFET器件的方法包括在第一极性的半导体层内形成第一沟槽，第一沟槽通常限定与第一极性相反的第二极性的阱区; 在原始半导体层上生长出第二极性的第一外延阱层; 在阱层上生长第一极性的第二外延源极接触层; 通过所述源极接触层和所述阱层的至少一部分形成第二沟槽; 在源极接触层上生长第二极性的第三外延层; 以及至少对所述第一外延层和所述第二外延层进行平坦化以暴露所述原始半导体层的上表面，其中所述第三外延层的顶表面在欧姆接触形成之前与所述源极接触层的顶表面基本共面。