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公开(公告)号：US08638624B2
公开(公告)日：2014-01-28
申请号：US13561248
申请日：2012-07-30
IPC分类号： G11C7/00
CPC分类号： G11C16/3427 , G11C11/5628 , G11C16/10 , G11C16/3418 , G11C27/02 , G11C2211/5642 , G11C2211/5646
摘要： Methods of programming a memory, memory devices, and systems are disclosed, for example. In one such method, each data line of a memory to be programmed is biased differently depending upon whether one or more of the data lines adjacent the data line are inhibited. In one such system, a connection circuit provides data corresponding to the inhibit status of a target data line to page buffers associated with data lines adjacent to the target data line.
摘要翻译： 例如，公开了存储器，存储器件和系统的编程方法。 在一种这样的方法中，根据是否禁止与数据线相邻的一条或多条数据线，要编程的存储器的每条数据线被不同地偏置。 在一个这样的系统中，连接电路将对应于目标数据线的禁止状态的数据提供给与与目标数据线相邻的数据线相关联的寻呼缓冲器。
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公开(公告)号：US08593876B2
公开(公告)日：2013-11-26
申请号：US13085611
申请日：2011-04-13
CPC分类号： G11C16/0483 , G11C16/26
摘要： Methods of operating memory devices, generating reference currents in memory devices, and sensing data states of memory cells in a memory device are disclosed. One such method includes generating reference currents utilized in sense amplifier circuitry to manage leakage currents while performing a sense operation within a memory device. Another such method activates one of two serially coupled transistors along with activating and deactivating the second transistor serially coupled with the first transistor thereby regulating a current through both serially coupled transistors and establishing a particular reference current.
摘要翻译： 公开了在存储器件中操作存储器件，产生存储器件中的参考电流以及感测存储器单元的数据状态的方法。 一种这样的方法包括产生在读出放大器电路中使用的参考电流，以在存储器件内进行感测操作的同时管理泄漏电流。 另一种这样的方法激活两个串联耦合晶体管中的一个，同时激活和去激活与第一晶体管串联耦合的第二晶体管，从而调节通过两个串联耦合的晶体管的电流并建立特定的参考电流。
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公开(公告)号：US20120243318A1
公开(公告)日：2012-09-27
申请号：US13072478
申请日：2011-03-25
IPC分类号： G11C16/10
CPC分类号： G11C16/34 , G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/3459
摘要： Some embodiments include a memory device and a method of programming memory cells of the memory device. One such method can include applying a signal to a line associated with a memory cell, the signal being generated based on digital information. The method can also include, while the signal is applied to the line, determining whether a state of the memory cell is near a target state when the digital information has a first value, and determining whether the state of the memory cell has reached the target state when the digital information has a second value. Other embodiments including additional memory devices and methods are described.
摘要翻译： 一些实施例包括存储器设备和编程存储器设备的存储器单元的方法。 一种这样的方法可以包括将信号施加到与存储器单元相关联的线，该信号是基于数字信息生成的。 该方法还可以包括当信号被施加到线路时，当数字信息具有第一值时，确定存储器单元的状态是否接近目标状态，并且确定存储器单元的状态是否已经达到目标 当数字信息具有第二值时状态。 描述包括附加存储器件和方法的其它实施例。
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公开(公告)号：US20120224429A1
公开(公告)日：2012-09-06
申请号：US13039778
申请日：2011-03-03
CPC分类号： G11C16/0483 , G11C16/06 , G11C16/3454
摘要： Methods for programming memory cells and memory devices are disclosed. One such method for programming includes performing a program verify operation of a group of memory cells. A number of potential CS2 situations are detected. If the number of detected potential CS2 situations is greater than a threshold, programming compensation for a CS2 situation is used in a subsequent programming operation.
摘要翻译： 公开了用于编程存储器单元和存储器件的方法。 一种用于编程的方法包括执行一组存储器单元的程序验证操作。 检测到一些潜在的CS2情况。 如果检测到的潜在CS2情况的数量大于阈值，则在随后的编程操作中使用针对CS2情况的编程补偿。
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公开(公告)号：US08194460B2
公开(公告)日：2012-06-05
申请号：US13173171
申请日：2011-06-30
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/3454
摘要： A selected memory cell on a selected word line is programmed through a plurality of programming pulses that are incremented by a step voltage. After a successful program verify operation, programming of the selected memory cell is inhibited while other memory cells of the selected word line are being programmed. Another program verify operation is performed on the selected memory cell. If the program verify operation fails, a bit line coupled to the selected cell is biased at the step voltage and a final programming pulse is issued to the selected word line. The selected memory cell is then locked from further programming without evaluating the final program verify operation.
摘要翻译： 所选字线上的所选择的存储单元通过增加阶跃电压的多个编程脉冲进行编程。 在成功的程序验证操作之后，所选存储单元的编程被禁止，同时所选字线的其它存储单元被编程。 对所选存储单元执行另一个程序验证操作。 如果程序验证操作失败，则耦合到所选单元的位线被偏置在阶跃电压上，并且向所选择的字线发出最终的编程脉冲。 然后，所选择的存储单元被锁定以进一步编程，而不评估最终程序验证操作。
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公开(公告)号：US20120081972A1
公开(公告)日：2012-04-05
申请号：US12896487
申请日：2010-10-01
CPC分类号： G11C16/3436 , G11C11/56 , G11C11/5628 , G11C16/00 , G11C16/06 , G11C16/10 , G11C16/24 , G11C16/3454 , G11C16/3481 , G11C2029/0409
摘要： Apparatus and methods for determining pass/fail condition of memories are disclosed. In at least one embodiment, a set of common lines, one for each rank of page buffers corresponding to a page, determine the pass/fail status of all connected memory cells, and the pass/fail status results for each line can be combined to determine a pass/fail for the page of memory.
摘要翻译： 公开了用于确定存储器的通过/失败状态的装置和方法。 在至少一个实施例中，对于与页面相对应的每个页面缓冲器等级的一组公共线路确定所有连接的存储器单元的通过/失败状态，并且可以将每行的通过/失败状态结果组合 确定内存页面的通过/失败。
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公开(公告)号：US20120075932A1
公开(公告)日：2012-03-29
申请号：US13313379
申请日：2011-12-07
IPC分类号： G11C16/10
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/3418 , G11C16/3427
摘要： In programming a selected word line of memory cells, a first program verify or read operation is performed, after one page of a selected word line is programmed, in order to determine a first quantity of memory cells that have been programmed to a predetermined reference point in the programmed first page distribution. Prior to programming the second page of the selected word line, a second program verify or read operation is performed to determine a second quantity of cells that are still at the reference point. The difference between the first and second quantities is an indication of the quantity of cells that experienced quick charge loss. The difference is used to determine an adjustment voltage for the second page verification operation after programming of the second page.
摘要翻译： 在编程存储器单元的选定字线时，在对所选字线的一页进行编程之后执行第一程序验证或读取操作，以便确定已被编程到预定参考点的第一数量的存储器单元 在编程的第一页分发。 在对所选字线的第二页进行编程之前，执行第二程序验证或读取操作以确定仍在参考点的第二数量的单元。 第一和第二数量之间的差异表示经历快速电荷损失的电池数量。 该差异用于在编程第二页之后确定用于第二页验证操作的调整电压。
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公开(公告)号：US08036035B2
公开(公告)日：2011-10-11
申请号：US12410696
申请日：2009-03-25
CPC分类号： G11C11/5635 , G11C16/10 , G11C16/3404 , G11C16/344 , G11C16/349 , G11C2211/5641
摘要： Memory devices and methods are disclosed to facilitate adjustment of program voltages applied during a program operation based upon erase operation cycle counter values stored in the memory device. In one such embodiment, an erase cycle counter is maintained for each block of a memory device and is stored in the associated block of memory. Programming voltage levels utilized during program operations of memory cells are determined, at least in part, based upon the value of the erase cycle counter stored in a memory block undergoing a programming operation, for example.
摘要翻译： 公开了存储器件和方法，以便于基于存储在存储器件中的擦除操作周期计数器值来调节在编程操作期间施加的编程电压。 在一个这样的实施例中，为存储器设备的每个块维护擦除周期计数器，并将其存储在相关的存储器块中。 至少部分地基于存储在经历编程操作的存储块中的擦除周期计数器的值来确定在存储器单元的编程操作期间使用的编程电压电平。
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19.发明授权Word line voltage boost system and method for non-volatile memory devices and memory devices and processor-based system using same 有权用于非易失性存储器件和存储器件的字线升压系统和方法以及使用它的基于处理器的系统公开(公告)号：US07924616B2
公开(公告)日：2011-04-12
申请号：US11795357
申请日：2007-05-04
IPC分类号： G11C16/04
摘要： The voltage of a selected word line is increased beyond the voltage to which a respective string driver transistor is capable of driving the word line by capacitively coupling a voltage to the selected word line from adjacent word lines. The voltage is capacitively coupled to the selected word line by increasing the voltages of the adjacent word lines after a programming voltage has been applied to a string driver transistor for the selected word line and after a string driver voltage has been applied to the gates of all of the string driver transistors in an array.
摘要翻译： 所选择的字线的电压通过从相邻字线电容耦合到所选字线的电压而增加到相应的串驱动晶体管能够驱动字线的电压。 在将编程电压施加到所选字线的串驱动晶体管之后，并且在将串驱动器电压施加到所有字的栅极之后，通过增加相邻字线的电压来将电压电容耦合到所选择的字线 的阵列驱动晶体管。
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20.发明申请Word Line Voltage Boost System and Method for Non-Volatile Memory Devices and Memory Devices and Processor-Based System Using Same 有权用于非易失性存储器件和存储器件的字线电压升压系统和方法以及使用其的基于处理器的系统公开(公告)号：US20100128534A1
公开(公告)日：2010-05-27
申请号：US11795357
申请日：2007-05-04
摘要： The voltage of a selected word line is increased beyond the voltage to which a respective string driver transistor is capable of driving the word line by capacitively coupling a voltage to the selected word line from adjacent word lines. The voltage is capacitively coupled to the selected word line by increasing the voltages of the adjacent word lines after a programming voltage has been applied to a string driver transistor for the selected word line and after a string driver voltage has been applied to the gates of all of the string driver transistors in an array.
摘要翻译： 所选择的字线的电压通过从相邻字线电容耦合到所选字线的电压而增加到相应的串驱动晶体管能够驱动字线的电压。 在将编程电压施加到所选字线的串驱动晶体管之后，并且在将串驱动器电压施加到所有字的栅极之后，通过增加相邻字线的电压来将电压电容耦合到所选字线 的阵列驱动晶体管。
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