公开(公告)号：US06635528B2

公开(公告)日：2003-10-21

申请号：US09741675

申请日：2000-12-19

申请人： Stephen R. Gilbert ,  Scott Summerfelt ,  Luigi Colombo

发明人： Stephen R. Gilbert ,  Scott Summerfelt ,  Luigi Colombo

IPC分类号： H01L2100

CPC分类号： H01L21/32139 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76849 ,  H01L21/7687 ,  H01L21/76877 ,  H01L27/11502 ,  H01L27/11507 ,  H01L28/55

摘要： An embodiment of the instant invention is a method of fabricating a planar conductive via in an opening through a dielectric layer having a top surface, a bottom surface and the opening having sides, the method comprising the steps of: depositing a first conductive material (114 of FIG. 7d) on the top surface of the dielectric layer and in the opening in the dielectric layer to substantially fill the opening with the conductive material; removing the portion of the first conductive material located on the dielectric layer and removing a portion of the first conductive material located in the opening in the dielectric layer to recess (406 of FIG. 7d) the first conductive material below the top surface of the dielectric layer; depositing a second conductive material (704 of FIG. 7d) in the recess to form a substantially planar top surface substantially coplanar with the top surface of the dielectric layer; and forming a third conductive material (302 of FIG. 7d) on the second conductive material, at least one of the second conductive material and the third conductive material acting as a diffusion barrier to prevent oxidation of the first conductive material.

摘要翻译： 本发明的一个实施例是一种在具有顶表面，底表面和开口具有侧面的电介质层的开口中制造平面导电通孔的方法，所述方法包括以下步骤：将第一导电材料（114 在电介质层的顶表面和电介质层的开口中，以基本上用导电材料填充开口; 去除位于电介质层上的第一导电材料的部分，并且去除位于电介质层中的开口中的第一导电材料的一部分以凹陷（图7d的406）第一导电材料在电介质顶表面下方 层; 在凹槽中沉积第二导电材料（图7d的704）以形成与介电层的顶表面基本上共面的基本平坦的顶表面; 以及在所述第二导电材料上形成第三导电材料（图7d的302），所述第二导电材料和所述第三导电材料中的至少一个用作扩散阻挡层以防止所述第一导电材料的氧化。

公开(公告)号：US06171898B2

公开(公告)日：2001-01-09

申请号：US09212031

申请日：1998-12-15

申请人： Darius Crenshaw ,  Scott Summerfelt

发明人： Darius Crenshaw ,  Scott Summerfelt

IPC分类号： H01L218242

CPC分类号： H01L27/10852 ,  H01L27/10814 ,  H01L28/55 ,  H01L28/75

摘要： A capacitor structure and method. The capacitor (12) comprises a HDC dielectric (40) and upper (44) and lower electrodes. The lower electrode comprises polysilicon(31-32), a diffusion barrier (34) on the polysilicon and an oxygen stable material (36) on the diffusion barrier (34). The oxygen stable material (36) is formed by first forming a disposable dielectric layer (50) patterned and etched to expose the area where the storage node is desired and then depositing the oxygen stable material (36). The oxygen stable material (36) is then either etched back or CMP processed using the disposable dielectric layer (50) as an endpoint. The disposable dielectric layer (50) is then removed. The HDC dielectric (40) is then formed adjacent the oxygen stable material (36).

摘要翻译： 电容器结构和方法。 电容器（12）包括HDC电介质（40）和上部（44）和下部电极。 下电极包括多晶硅（31-32），多晶硅上的扩散阻挡层（34）和扩散阻挡层（34）上的氧稳定材料（36）。 氧稳定材料（36）通过首先形成图案化和蚀刻的一次性介电层（50）来形成，以暴露存储节点所需的区域，然后沉积氧稳定材料（36）。 然后使用一次性介电层（50）作为终点，将氧稳定材料（36）进行回蚀刻或CMP处理。 然后去除一次性介电层（50）。 然后，HDC电介质（40）邻近氧稳定材料（36）形成。

公开(公告)号：US05998225A

公开(公告)日：1999-12-07

申请号：US212041

申请日：1998-12-15

申请人： Darius Crenshaw ,  Scott Summerfelt

发明人： Darius Crenshaw ,  Scott Summerfelt

IPC分类号： H01L21/02 ,  H01L21/8242 ,  H01G7/06

CPC分类号： H01L27/10852 ,  H01L28/55 ,  H01L28/56

摘要： A capacitor structure and method. The capacitor (12) comprises a HDC dielectric (40) and upper (44) and lower electrodes. The lower electrode comprises polysilicon(31-32), a diffusion barrier (34) on the polysilicon and an oxygen stable material (36) on the diffusion barrier (34). The diffusion barrier (34) is deposited followed by the deposition of a temporary dielectric layer (50). The temporary dielectric layer (50) is then patterned and etched to expose the area where the storage node is desired. Next, the oxygen stable material (36) is deposited. The oxygen stable material (36) is then either etched back or CMP processed using the temporary dielectric layer (50) as an endpoint. The temporary dielectric layer (50) is then removed along with the exposed portions of diffusion barrier (34). The HDC dielectric (40) is then formed adjacent the oxygen stable material (36).

摘要翻译： 电容器结构和方法。 电容器（12）包括HDC电介质（40）和上部（44）和下部电极。 下电极包括多晶硅（31-32），多晶硅上的扩散阻挡层（34）和扩散阻挡层（34）上的氧稳定材料（36）。 沉积扩散阻挡层（34），随后沉积临时介电层（50）。 然后对临时介电层（50）进行图案化和蚀刻以暴露存储节点所期望的区域。 接下来，沉积氧稳定材料（36）。 然后使用临时介电层（50）作为端点对氧稳定材料（36）进行回蚀刻或CMP处理。 然后将临时介电层（50）与扩散屏障（34）的暴露部分一起去除。 然后，HDC电介质（40）邻近氧稳定材料（36）形成。

公开(公告)号：US20120170348A1

公开(公告)日：2012-07-05

申请号：US13240252

申请日：2011-09-22

申请人： Michael Patrick Clinton ,  Steven Craig Bartling ,  Scott Summerfelt ,  Hugh McAdams

发明人： Michael Patrick Clinton ,  Steven Craig Bartling ,  Scott Summerfelt ,  Hugh McAdams

IPC分类号： G11C11/22

CPC分类号： G11C11/22

摘要： A self-timed sense amplifier read buffer pulls down a pre-charged high global bit line, which then feeds data into a tri state write back buffer that is connected directly to the bit line. The bit line provides charge to a ferroelectric capacitor to write a logical “one” or “zero” while by-passing an isolator switch disposed between the sense amplifier and the ferroelectric capacitor. Because the sense amplifier uses grounded bit line sensing, the read buffer will not start pulling down the global bit line until after the sense amplifier signal amplification, which makes the timing of the control signal for this read buffer non-critical. The write-back buffer enable timing is also self-timed off of the sense amplifier. Therefore, the read data write-back to a ferroelectric memory cell is locally controlled and begins quickly after reading data from the ferroelectric memory cell, thereby allowing a quick cycle time.

摘要翻译： 自定时读出放大器读缓冲器拉低预充电的高全局位线，然后将数据馈送到直接连接到位线的三态回写缓冲器。 该位线向强电介质电容器充电以在绕过感测放大器和铁电电容器之间的隔离开关旁路时写入逻辑“1”或“0”。 由于读出放大器使用接地位线检测，所以读缓冲器不会开始下拉全局位线直到读出放大器信号放大，这使得该读缓冲器的控制信号的定时非关键。 回写缓冲器使能定时也是从读出放大器自定时的。 因此，读取到强电介质存储单元的数据被局部控制，并且在从铁电存储单元读取数据之后迅速开始，从而允许快速循环时间。

公开(公告)号：US20070221974A1

公开(公告)日：2007-09-27

申请号：US11756372

申请日：2007-05-31

申请人： Francis Celii ,  Mahesh Thakre ,  Scott Summerfelt

发明人： Francis Celii ,  Mahesh Thakre ,  Scott Summerfelt

IPC分类号： H01L29/94

CPC分类号： H01L28/55 ,  H01L21/31122 ,  H01L21/32136 ,  H01L28/75

摘要： A ferroelectric memory capacitor is formed by forming a barrier layer, a first metal layer, a ferroelectric layer, a second metal layer, and a hard mask layer, on dielectric layer (70). Using the patterned hard mask layer (255), the layers are etched to form an etched barrier layer (205), and etched first metal layer (215), and etched ferroelectric layer (225), and etched second metal layers (235, 245). The etched layers form a ferroelectric memory capacitor (270) with sidewalls that form an angle with the plane of the upper surface of the dielectric layer (70) between 78° and 88°. The processes used to etch the layers are plasma processes performed at temperatures between 200° C. and 500° C.

摘要翻译： 在电介质层（70）上形成阻挡层，第一金属层，铁电体层，第二金属层和硬掩模层，形成铁电存储电容器。 使用图案化的硬掩模层（255），蚀刻这些层以形成蚀刻的阻挡层（205），蚀刻第一金属层（215）和蚀刻铁电层（225），并蚀刻第二金属层 ）。 蚀刻层形成具有与电介质层（70）的上表面的平面形成角度为78°至88°的侧壁的铁电存储电容器（270）。 用于蚀刻层的工艺是在200℃和500℃之间的温度下进行的等离子体处理。

公开(公告)号：US20050227378A1

公开(公告)日：2005-10-13

申请号：US11145663

申请日：2005-06-06

申请人： Theodore Moise ,  Guoqiang Xing ,  Mark Visokay ,  Justin Gaynor ,  Stephen Gilbert ,  Francis Celii ,  Scott Summerfelt ,  Luigi Colombo

发明人： Theodore Moise ,  Guoqiang Xing ,  Mark Visokay ,  Justin Gaynor ,  Stephen Gilbert ,  Francis Celii ,  Scott Summerfelt ,  Luigi Colombo

IPC分类号： H01L21/02 ,  H01L21/311 ,  H01L21/768 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/108 ,  H01L27/115

CPC分类号： H01L27/11502 ,  H01L21/31116 ,  H01L21/76895 ,  H01L27/10811 ,  H01L27/10814 ,  H01L27/10852 ,  H01L27/11507 ,  H01L28/55

摘要： A via etch to contact a capacitor with ferroelectric between electrodes together with dielectric on an insulating diffusion barrier includes two-step etch with F-based dielectric etch and Cl- and F-based barrier etch.

公开(公告)号：US20050205911A1

公开(公告)日：2005-09-22

申请号：US11033224

申请日：2005-01-11

申请人： K. Udayakumar ,  Theodore Moise ,  Scott Summerfelt

发明人： K. Udayakumar ,  Theodore Moise ,  Scott Summerfelt

IPC分类号： H01L27/105 ,  H01L21/02 ,  H01L21/8246 ,  H01L29/76 ,  H01L29/94

CPC分类号： H01L27/11507 ,  H01L28/57

摘要： Hydrogen barriers and fabrication methods are provided for protecting ferroelectric capacitors (CFE) from hydrogen diffusion in semiconductor devices (102), wherein nitrided aluminum oxide (N—AlOx) is formed over a ferroelectric capacitor (CFE), and one or more silicon nitride layers (112, 117) are formed over the nitrided aluminum oxide (N—AlOx). Hydrogen barriers are also provided in which an aluminum oxide (AlOx, N—AlOx) is formed over the ferroelectric capacitors (CFE), with two or more silicon nitride layers (112, 117) formed over the aluminum oxide (AlOx, N—AlOx), wherein the second silicon nitride layer (112) comprises a low silicon-hydrogen SiN material.

摘要翻译： 提供氢屏障和制造方法用于在半导体器件（102）中保护铁电电容器（C LIMIT）免受氢扩散，其中氮化的氧化铝（N-AlOx）形成在铁电电容器（C < 在氮化的氧化铝（N-AlOx）上形成一个或多个氮化硅层（112,117）。 还提供了氢屏障，其中在铁电电容器（CFE）上形成氧化铝（AlOx，N-AlOx），其上形成有两个或更多个氮化硅层（112,117） 氧化铝（AlOx，N-AlOx），其中第二氮化硅层（112）包括低硅氢SiN材料。

公开(公告)号：US20050145908A1

公开(公告)日：2005-07-07

申请号：US10749668

申请日：2003-12-30

申请人： Theodore Moise ,  Scott Summerfelt ,  K.R. Udayakumar

发明人： Theodore Moise ,  Scott Summerfelt ,  K.R. Udayakumar

IPC分类号： H01L21/02 ,  H01L21/8246 ,  H01L27/115 ,  H01L21/00 ,  H01L29/76

CPC分类号： H01L27/11502 ,  H01L27/11507 ,  H01L28/55

摘要： One aspect of the invention relates to a method of manufacturing an integrated circuit comprising forming an array of ferroelectric memory cells on a semiconductor substrate, heating the substrate to a temperature near a Curie temperature of the ferroelectric cores, and subjecting the substrate to a temperature program, whereby thermally induced stresses on the ferroelectric cores cause a switched polarization of the cores to increase by at least about 25% as the cores cool to about room temperature. Embodiments of the invention include metal filled vias of expanded cross-section above and below the ferroelectric cores, which increase the thermal stresses on the ferroelectic cores during cooling.

摘要翻译： 本发明的一个方面涉及一种制造集成电路的方法，包括在半导体衬底上形成铁电存储器单元的阵列，将衬底加热到​​铁电芯的居里温度附近的温度，并对衬底进行温度程序 ，由此当铁芯冷却至约室温时，铁电芯上的热诱导应力使芯的开关极化增加至少约25％。 本发明的实施例包括在铁电芯上方和下方的膨胀横截面的金属填充通孔，其在冷却期间增加铁电芯上的热应力。

公开(公告)号：US20050032301A1

公开(公告)日：2005-02-10

申请号：US10635994

申请日：2003-08-07

申请人： K. Udayakumar ,  Maritin Albrecht ,  Theodore Moise ,  Scott Summerfelt ,  Sarah Hartwig

发明人： K. Udayakumar ,  Maritin Albrecht ,  Theodore Moise ,  Scott Summerfelt ,  Sarah Hartwig

IPC分类号： H01L21/02 ,  H01L21/318 ,  H01L21/768 ,  H01L21/8246 ,  H01L27/115 ,  H01L21/8242 ,  H01L21/31 ,  H01L21/00 ,  H01L21/469

CPC分类号： H01L21/76829 ,  H01L21/3185 ,  H01L21/76828 ,  H01L21/76832 ,  H01L21/76834 ,  H01L27/11502 ,  H01L27/11507 ,  H01L28/57

摘要： Semiconductor devices and fabrication methods are disclosed, in which one or more low silicon-hydrogen SiN barriers are provided to inhibit hydrogen diffusion into ferroelectric capacitors and into transistor gate dielectric interface areas. The barriers may be used as etch stop layers in various levels of the semiconductor device structure above and/or below the level at which the ferroelectric capacitors are formed so as to reduce the hydrogen related degradation of the switched polarization properties of the ferroelectric capacitors and to reduce negative bias temperature instability in the device transistors.

摘要翻译： 公开了半导体器件和制造方法，其中提供一个或多个低硅氢SiN栅极以阻止氢扩散到铁电电容器中并进入晶体管栅极电介质界面区域。 可以将阻挡层用作在形成强电介质电容器的电平以上和/或以下的半导体器件结构的各种级别的蚀刻停止层，以便降低铁电电容器的开关极化特性的氢相关劣化，并且 降低器件晶体管的负偏压温度不稳定性。

公开(公告)号：US06709875B2

公开(公告)日：2004-03-23

申请号：US09925201

申请日：2001-08-08

申请人： Stephen R. Gilbert ,  Trace Q. Hurd ,  Laura W. Mirkarimi ,  Scott Summerfelt ,  Luigi Colombo

发明人： Stephen R. Gilbert ,  Trace Q. Hurd ,  Laura W. Mirkarimi ,  Scott Summerfelt ,  Luigi Colombo

IPC分类号： H01G706

CPC分类号： H01L21/6708 ,  H01L21/31122 ,  H01L21/32136 ,  H01L27/0805 ,  H01L27/11502 ,  H01L28/55

摘要： A ferroelectric device fabrication process is described in which ferroelectric device contaminant substances (e.g., Pb, Zr, Ti, and Ir) that are incompatible with standard CMOS fabrication processes are tightly controlled. In particular, specific etch chemistries have been developed to remove incompatible substances from the backside and edge surfaces of the substrate after a ferroelectric device has been formed. In addition, a sacrificial layer may be disposed over the bottom and edge surfaces (and, in some embodiments, the frontside edge exclusion zone surface) of the substrate to assist in the removal of difficult-to-etch contaminants (e.g., Ir). In this way, the ferroelectric device fabrication process may be integrated with a standard semiconductor fabrication process, whereby ferroelectric devices may be formed together with semiconductor integrated circuits without substantial risk of cross-contamination through shared equipment (e.g., steppers, metrology tools, and the like).

摘要翻译： 描述了与标准CMOS制造工艺不兼容的铁电体器件污染物质（例如，Pb，Zr，Ti和Ir）被严格控制的铁电器件制造工艺。 特别地，已经开发了特定的蚀刻化学物质，以在形成铁电体器件之后从衬底的背面和边缘表面去除不相容的物质。 此外，牺牲层可以设置在衬底的底部和边缘表面（以及在一些实施例中，前侧边缘排除区域表面）之上，以帮助去除难以蚀刻的污染物（例如Ir）。 以这种方式，铁电体器件的制造工艺可以与标准的半导体制造工艺集成在一起，由此铁电器件可以与半导体集成电路一起形成，而没有通过共享设备（例如，步进器，计量工具和 喜欢）。