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    Contamination control for embedded ferroelectric device fabrication processes
    1.
    发明授权
    Contamination control for embedded ferroelectric device fabrication processes 失效
    嵌入式铁电元件制造工艺的污染控制

    公开(公告)号：US06709875B2

    公开(公告)日：2004-03-23

    申请号：US09925201

    申请日：2001-08-08

    申请人： Stephen R. Gilbert ,  Trace Q. Hurd ,  Laura W. Mirkarimi ,  Scott Summerfelt ,  Luigi Colombo

    发明人： Stephen R. Gilbert ,  Trace Q. Hurd ,  Laura W. Mirkarimi ,  Scott Summerfelt ,  Luigi Colombo

    IPC分类号： H01G706

    CPC分类号： H01L21/6708 ,  H01L21/31122 ,  H01L21/32136 ,  H01L27/0805 ,  H01L27/11502 ,  H01L28/55

    摘要： A ferroelectric device fabrication process is described in which ferroelectric device contaminant substances (e.g., Pb, Zr, Ti, and Ir) that are incompatible with standard CMOS fabrication processes are tightly controlled. In particular, specific etch chemistries have been developed to remove incompatible substances from the backside and edge surfaces of the substrate after a ferroelectric device has been formed. In addition, a sacrificial layer may be disposed over the bottom and edge surfaces (and, in some embodiments, the frontside edge exclusion zone surface) of the substrate to assist in the removal of difficult-to-etch contaminants (e.g., Ir). In this way, the ferroelectric device fabrication process may be integrated with a standard semiconductor fabrication process, whereby ferroelectric devices may be formed together with semiconductor integrated circuits without substantial risk of cross-contamination through shared equipment (e.g., steppers, metrology tools, and the like).

    摘要翻译： 描述了与标准CMOS制造工艺不兼容的铁电体器件污染物质（例如，Pb，Zr，Ti和Ir）被严格控制的铁电器件制造工艺。 特别地，已经开发了特定的蚀刻化学物质，以在形成铁电体器件之后从衬底的背面和边缘表面去除不相容的物质。 此外，牺牲层可以设置在衬底的底部和边缘表面（以及在一些实施例中，前侧边缘排除区域表面）之上，以帮助去除难以蚀刻的污染物（例如Ir）。 以这种方式，铁电体器件的制造工艺可以与标准的半导体制造工艺集成在一起，由此铁电器件可以与半导体集成电路一起形成，而没有通过共享设备（例如，步进器，计量工具和 喜欢）。

    Method of planarizing a conductive plug situated under a ferroelectric capacitor
    3.
    发明授权
    Method of planarizing a conductive plug situated under a ferroelectric capacitor 有权
    平面化位于铁电电容器下方的导电插塞的方法

    公开(公告)号：US06635528B2

    公开(公告)日：2003-10-21

    申请号：US09741675

    申请日：2000-12-19

    申请人： Stephen R. Gilbert ,  Scott Summerfelt ,  Luigi Colombo

    发明人： Stephen R. Gilbert ,  Scott Summerfelt ,  Luigi Colombo

    IPC分类号： H01L2100

    CPC分类号： H01L21/32139 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76849 ,  H01L21/7687 ,  H01L21/76877 ,  H01L27/11502 ,  H01L27/11507 ,  H01L28/55

    摘要： An embodiment of the instant invention is a method of fabricating a planar conductive via in an opening through a dielectric layer having a top surface, a bottom surface and the opening having sides, the method comprising the steps of: depositing a first conductive material (114 of FIG. 7d) on the top surface of the dielectric layer and in the opening in the dielectric layer to substantially fill the opening with the conductive material; removing the portion of the first conductive material located on the dielectric layer and removing a portion of the first conductive material located in the opening in the dielectric layer to recess (406 of FIG. 7d) the first conductive material below the top surface of the dielectric layer; depositing a second conductive material (704 of FIG. 7d) in the recess to form a substantially planar top surface substantially coplanar with the top surface of the dielectric layer; and forming a third conductive material (302 of FIG. 7d) on the second conductive material, at least one of the second conductive material and the third conductive material acting as a diffusion barrier to prevent oxidation of the first conductive material.

    摘要翻译： 本发明的一个实施例是一种在具有顶表面，底表面和开口具有侧面的电介质层的开口中制造平面导电通孔的方法，所述方法包括以下步骤：将第一导电材料（114 在电介质层的顶表面和电介质层的开口中，以基本上用导电材料填充开口; 去除位于电介质层上的第一导电材料的部分，并且去除位于电介质层中的开口中的第一导电材料的一部分以凹陷（图7d的406）第一导电材料在电介质顶表面下方 层; 在凹槽中沉积第二导电材料（图7d的704）以形成与介电层的顶表面基本上共面的基本平坦的顶表面; 以及在所述第二导电材料上形成第三导电材料（图7d的302），所述第二导电材料和所述第三导电材料中的至少一个用作扩散阻挡层以防止所述第一导电材料的氧化。

    Method of fabricating a ferroelectric memory cell
    7.
    发明授权
    Method of fabricating a ferroelectric memory cell 有权
    制造铁电存储单元的方法

    公开(公告)号：US06548343B1

    公开(公告)日：2003-04-15

    申请号：US09702985

    申请日：2000-10-31

    申请人： Scott R. Summerfelt ,  Theodore S. Moise ,  Guoqiang Xing ,  Luigi Colombo ,  Tomoyuki Sakoda ,  Stephen R. Gilbert ,  Alvin L. S. Loke ,  Shawming Ma ,  Rahim Kavari ,  Laura Wills-Mirkarimi ,  Jun Amano

    发明人： Scott R. Summerfelt ,  Theodore S. Moise ,  Guoqiang Xing ,  Luigi Colombo ,  Tomoyuki Sakoda ,  Stephen R. Gilbert ,  Alvin L. S. Loke ,  Shawming Ma ,  Rahim Kavari ,  Laura Wills-Mirkarimi ,  Jun Amano

    IPC分类号： H01L218242

    CPC分类号： H01L27/11502 ,  H01L27/11507 ,  H01L28/57

    摘要： An embodiment of the instant invention is a method of fabricating a ferroelectric capacitor which is situated over a structure, the method comprising the steps of: forming a bottom electrode on the structure (124 of FIG. 1), the bottom electrode having a top surface and sides; forming a capacitor dielectric (126 of FIG. 1) comprised of a ferroelectric material on the bottom electrode, the capacitor dielectric having a top surface and sides; forming a top electrode (128 and 130 of FIG. 1) on the capacitor dielectric, the top electrode having a top surface and sides, the ferroelectric capacitor is comprised of the bottom electrode, the capacitor dielectric, and the top electrode; forming a barrier layer (118 and 120 of FIG. 1) on the side of the bottom electrode, the side of the capacitor dielectric, and the side of the top electrode; forming a dielectric layer on the barrier layer and the structure, the dielectric having a top surface and a bottom surface; and performing a thermal step for a duration at a temperature between 400 and 900 C. in an ambient comprised of a gas selected from the group consisting of: argon, nitrogen, and a combination thereof, the step of performing a thermal step being performed after the step of forming the barrier layer.

    摘要翻译： 本发明的一个实施例是制造位于结构上方的铁电电容器的方法，所述方法包括以下步骤：在所述结构（图1的124）上形成底电极，所述底电极具有顶表面 和边; 在底部电极上形成由铁电材料构成的电容器电介质（图1的126），电容器电介质具有顶表面和侧面; 在电容器电介质上形成顶电极（图1的128和130），顶电极具有顶表面和侧面，铁电电容器由底电极，电容器电介质和顶电极组成; 在底电极侧，电容器电介质侧和顶电极侧形成阻挡层（图1的118和120）; 在所述阻挡层和所述结构上形成电介质层，所述电介质具有顶表面和底表面; 并且在由选自氩，氮及其组合的气体组成的环境中在400-900℃的温度下进行热步骤，所述环境包括：在步骤 形成阻挡层的步骤。

    Hardmask designs for dry etching FeRAM capacitor stacks
    9.
    发明授权
    Hardmask designs for dry etching FeRAM capacitor stacks 有权
    硬掩模设计用于干蚀刻FeRAM电容器堆叠

    公开(公告)号：US06534809B2

    公开(公告)日：2003-03-18

    申请号：US09741479

    申请日：2000-12-19

    申请人： Theodore Moise ,  Stephen R. Gilbert ,  Scott R. Summerfelt ,  Guoqiang Xing ,  Luigi Colombo

    发明人： Theodore Moise ,  Stephen R. Gilbert ,  Scott R. Summerfelt ,  Guoqiang Xing ,  Luigi Colombo

    IPC分类号： H01L2994

    CPC分类号： H01L28/55 ,  H01L21/31122 ,  H01L21/31144 ,  H01L21/32136 ,  H01L21/32139

    摘要： An embodiment of the instant invention is a ferroelectric capacitor formed over a semiconductor substrate, the ferroelectric capacitor comprising: a bottom electrode formed over the semiconductor substrate, the bottom electrode comprised of a bottom electrode material (304 of FIG. 4a); a top electrode formed over the bottom electrode and comprised of a first electrode material (306and 308 of FIG. 4a); a ferroelectric material (306 of FIG. 4a) situated between the top electrode and the bottom electrode; and a hardmask formed on the top electrode and comprising a bottom hardmask layer (402 of FIG. 4a) and a top hardmask layer (408 of FIG. 4a) formed on the bottom hardmask layer, the top hardmask layer able to with stand etchants used to etch the bottom electrode, the top electrode, and the ferroelectric material to leave the bottom hardmask layer substantially unremoved during the etch and the bottom hardmask layer being comprised of a conductive material which substantially acts as a hydrogen diffusion barrier.

    摘要翻译： 本发明的一个实施方案是形成在半导体衬底上的铁电电容器，所述铁电电容器包括：形成在所述半导体衬底上的底部电极，所述底部电极由底部电极材料（图4a的304）组成; 形成在底部电极上并由第一电极材料（图4a的306和308）组成的顶部电极; 位于顶部电极和底部电极之间的铁电材料（图4a的306） 以及形成在顶部电极上并包括底部硬掩模层（图4a的402）和形成在底部硬掩模层上的顶部硬掩模层（图4a的408）的硬掩模，所述顶部硬掩模层能够使用支架蚀刻剂 蚀刻底部电极，顶部电极和铁电材料以使蚀刻期间底部硬掩模层基本上不被去除，并且底部硬掩模层由基本上充当氢扩散阻挡层的导电材料构成。