公开(公告)号：US07211483B2

公开(公告)日：2007-05-01

申请号：US11068173

申请日：2005-02-28

申请人： Yi-Nan Chen ,  Hui-Min Mao ,  Chih-Yuan Hsiao ,  Ming-Cheng Chang

发明人： Yi-Nan Chen ,  Hui-Min Mao ,  Chih-Yuan Hsiao ,  Ming-Cheng Chang

IPC分类号： H01L21/8242

CPC分类号： H01L27/10864 ,  H01L27/10867

摘要： A memory device with vertical transistors and deep trench capacitors. The device includes a substrate containing at least one deep trench and a capacitor deposited in the lower portion of the deep trench. A conducting structure, having a first conductive layer and a second conductive layer, is deposited on the trench capacitor. A ring shaped insulator is deposited on the sidewall and between the substrate and the first conductive layer. The first conductive layer is surrounded by the ring shaped insulator, and the second conductive layer is deposited on the first conductive layer and the ring shaped insulator. A diffusion barrier between the second conductive layer and the substrate of the deep trench is deposited on one side of the sidewall of the deep trench. A TTO is deposited on the conducting structure. A control gate is deposited on the TTO.

摘要翻译： 具有垂直晶体管和深沟槽电容器的存储器件。 该器件包括含有至少一个深沟槽和沉积在深沟槽的下部的电容器的衬底。 具有第一导电层和第二导电层的导电结构沉积在沟槽电容器上。 环形绝缘体沉积在侧壁上以及衬底和第一导电层之间。 第一导电层被环形绝缘体包围，并且第二导电层沉积在第一导电层和环形绝缘体上。 在深沟槽的侧壁的一侧上沉积第二导电层和深沟槽的衬底之间的扩散阻挡层。 TTO沉积在导电结构上。 控制门被存放在TTO上。

公开(公告)号：US07105453B2

公开(公告)日：2006-09-12

申请号：US10783467

申请日：2004-02-20

申请人： Yi-Nan Chen ,  Tse-Yao Huang ,  Hui-Min Mao

发明人： Yi-Nan Chen ,  Tse-Yao Huang ,  Hui-Min Mao

IPC分类号： H01L21/302 ,  H01L21/3065

CPC分类号： H01L21/76844 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76897

摘要： A method of forming contact holes. A substrate on which a plurality of gate structures is formed is provided, wherein the gate structure comprises a gate, a gate capping layer, and a gate spacer. An insulating layer is formed on the gate structures and fills between the gate structures. The insulating layer is etched using the gate capping layers, the gate spacers, and the substrate as stop layers to form first contact holes between the gate structures to expose the substrate and the gate spacers and form second contact holes overlying each gate structure to expose the gate capping layers. A protective spacer is formed over each sidewall of the first contact holes and the second contact holes. The gate capping layer under each gate contact hole is etched using the protective spacer as a stop layer to expose the gate. The protective spacers are removed.

摘要翻译： 一种形成接触孔的方法。 提供形成有多个栅极结构的基板，其中栅极结构包括栅极，栅极覆盖层和栅极间隔物。 在栅极结构上形成绝缘层，并填充在栅极结构之间。 使用栅极覆盖层，栅极间隔物和衬底作为停止层来蚀刻绝缘层，以在栅极结构之间形成第一接触孔，以暴露衬底和栅极间隔物，并形成覆盖每个栅极结构的第二接触孔，以暴露出 门盖层。 在第一接触孔和第二接触孔的每个侧壁上形成保护隔离物。 在每个栅极接触孔下方的栅极覆盖层使用保护隔板作为停止层进行蚀刻，以露出栅极。 去除保护性间隔物。

公开(公告)号：US20060118886A1

公开(公告)日：2006-06-08

申请号：US11338330

申请日：2006-01-23

申请人： Tzu-Ching Tsai ,  Yi-Nan Chen ,  Hui-Min Mao

发明人： Tzu-Ching Tsai ,  Yi-Nan Chen ,  Hui-Min Mao

IPC分类号： H01L29/772

CPC分类号： H01L21/76897 ,  H01L21/76829 ,  H01L21/76895

摘要： A method of forming a bit line contact via. The method includes providing a substrate having a transistor with a gate electrode, drain region, and source region, forming a conductive layer overlying the drain region, conformally forming an insulating barrier layer overlying the substrate, blanketly forming a dielectric layer overlying the insulating barrier layer, and forming a via through the dielectric layer and insulating barrier layer, exposing the conductive layer.

摘要翻译： 形成位线接触通孔的方法。 该方法包括提供具有晶体管的衬底，该晶体管具有栅极，漏极区和源极区，形成覆盖漏极区的导电层，保形地形成覆盖衬底的绝缘阻挡层，覆盖在绝缘阻挡层上的绝缘层 并且通过介电层和绝缘阻挡层形成通孔，暴露导电层。

公开(公告)号：US20050001256A1

公开(公告)日：2005-01-06

申请号：US10691173

申请日：2003-10-22

申请人： Yi-Nan Chen ,  Hui-Min Mao ,  Chih-Yuan Hsiao ,  Ming-Cheng Chang

发明人： Yi-Nan Chen ,  Hui-Min Mao ,  Chih-Yuan Hsiao ,  Ming-Cheng Chang

IPC分类号： H01L21/8242 ,  H01L27/108 ,  H01L29/76 ,  H01L31/119

CPC分类号： H01L27/10864 ,  H01L27/10867

摘要： A memory device with vertical transistors and deep trench capacitors. The device includes a substrate containing at least one deep trench and a capacitor deposited in the lower portion of the deep trench. A conducting structure, having a first conductive layer and a second conductive layer, is deposited on the trench capacitor. A ring shaped insulator is deposited on the sidewall and between the substrate and the first conductive layer. The first conductive layer is surrounded by the ring shaped insulator, and the second conductive layer is deposited on the first conductive layer and the ring shaped insulator. A diffusion barrier between the second conductive layer and the substrate of the deep trench is deposited on one side of the sidewall of the deep trench. A TTO is deposited on the conducting structure. A control gate is deposited on the TTO.

公开(公告)号：US06790765B1

公开(公告)日：2004-09-14

申请号：US10720275

申请日：2003-11-25

申请人： Tse-Yao Huang ,  Yi-Nan Chen ,  Hui-Min Mao

发明人： Tse-Yao Huang ,  Yi-Nan Chen ,  Hui-Min Mao

IPC分类号： H01L214763

CPC分类号： H01L21/76897 ,  H01L27/1052 ,  H01L27/11521

摘要： A method for forming contacts on a semiconductor device is provided. The method includes steps of forming an opening on a gate contact area, depositing a dielectric layer on a bit-line contact area and the opening, coating a photoresist to etch the dielectric layer, removing the photoresist and finally forming a conductive layer on a bit-line contact opening and a gate contact opening.

摘要翻译： 提供了一种用于在半导体器件上形成接触的方法。 该方法包括以下步骤：在栅极接触区域上形成开口，在位线接触区域上沉积介电层和开口，涂覆光致抗蚀剂以蚀刻电介质层，去除光致抗蚀剂并最终在一个位上形成导电层 线接触开口和门接触开口。

公开(公告)号：US06790735B2

公开(公告)日：2004-09-14

申请号：US10449297

申请日：2003-05-29

申请人： Hui-Min Mao ,  Sheng-Tsung Chen ,  Yi-Nan Chen ,  Bo-Ching Jiang ,  Chih-Yuan Hsiao

发明人： Hui-Min Mao ,  Sheng-Tsung Chen ,  Yi-Nan Chen ,  Bo-Ching Jiang ,  Chih-Yuan Hsiao

IPC分类号： H01L21336

CPC分类号： H01L27/10894 ,  H01L27/105 ,  H01L27/11 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： A method of forming source/drain regions in semiconductor devices. First, a substrate having at least one gate structure is provided. Next, first, second, and third insulating spacers are successively formed over the sidewall of the gate structure. Subsequently, ion implantation is performed on the substrate on both sides of the gate structure using the third insulating spacer as a mask to form first doping regions. After the third insulating spacer is removed, ion implantation is performed on the substrate on both sides of the gate structure using the second insulating spacer as a mask to form second doping regions serving as source/drain regions with the first doping regions. Finally, after the second insulating spacer is removed, ion implantation is performed on the substrate on both sides of the gate structure using the first insulating spacer as a mask to form third doping regions, thereby preventing punchthrough.

公开(公告)号：US20070099125A1

公开(公告)日：2007-05-03

申请号：US11564238

申请日：2006-11-28

申请人： Yi-Nan Chen ,  Jeng-Ping Lin ,  Chih-Ching Lin ,  Hui-Min Mao

发明人： Yi-Nan Chen ,  Jeng-Ping Lin ,  Chih-Ching Lin ,  Hui-Min Mao

IPC分类号： G03C5/00

CPC分类号： H01L21/76897 ,  H01L21/76885 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10888

摘要： A fabrication method for a damascene bit line contact plug. A semiconductor substrate has a first gate conductive structure, a second gate conductive structure and a source/drain region formed therebetween. A first conductive layer is formed in a space between the first gate conductive structure and the second gate conductive structure to be electrically connected to the source/drain region. An inter-layer dielectric with a planarized surface is formed to cover the first conductive layer, the first gate conductive structure, and the second gate conductive structure. A bit line contact hole is formed in the inter-layer dielectric to expose the top of the first conductive layer. A second conductive layer is formed in the bit line contact hole, in which the combination of the second conductive layer and the first conductive layer serves as a damascene bit line contact plug.

摘要翻译： 镶嵌位线接触插头的制造方法。 半导体衬底具有形成在其间的第一栅极导电结构，第二栅极导电结构和源极/漏极区。 第一导电层形成在第一栅极导电结构和第二栅极导电结构之间的空间中，以电连接到源极/漏极区。 形成具有平坦化表面的层间电介质以覆盖第一导电层，第一栅极导电结构和第二栅极导电结构。 在层间电介质中形成位线接触孔，露出第一导电层的顶部。 第二导电层形成在位线接触孔中，其中第二导电层和第一导电层的组合用作镶嵌位线接触插塞。

公开(公告)号：US06977134B2

公开(公告)日：2005-12-20

申请号：US10452274

申请日：2003-06-02

申请人： Chung-Peng Hao ,  Hui-Min Mao ,  Yi-Nan Chen ,  Tzu-Ching Tsai

发明人： Chung-Peng Hao ,  Hui-Min Mao ,  Yi-Nan Chen ,  Tzu-Ching Tsai

IPC分类号： H01L21/336 ,  G03C5/00

CPC分类号： H01L29/66583

摘要： A manufacturing method for a MOSFET gate structure. The method comprises providing a substrate, sequentially depositing a pad layer and a dielectric layer thereon, defining a gate trench passing through the dielectric layer and the pad layer to expose a predetermined gate area of the substrate, sequentially forming a gate dielectric layer, a first conductive layer, a second conductive layer, and a cap layer on the exposed substrate in the gate trench to form a damascene gate structure, and removing the dielectric layer.

摘要翻译： 一种用于MOSFET栅极结构的制造方法。 该方法包括提供衬底，在其上依次沉积衬垫层和电介质层，限定通过介电层和焊盘层的栅极沟槽，以暴露衬底的预定栅极区域，顺序地形成栅极电介质层，第一 导电层，第二导电层和盖层，以形成镶嵌栅极结构，并去除介电层。

公开(公告)号：US20050275107A1

公开(公告)日：2005-12-15

申请号：US10923591

申请日：2004-08-20

申请人： Yi-Nan Chen ,  Hui-Min Mao

发明人： Yi-Nan Chen ,  Hui-Min Mao

IPC分类号： G03F9/00 ,  H01L21/00 ,  H01L21/311 ,  H01L21/4763 ,  H01L21/768 ,  H01L23/544

CPC分类号： H01L21/31144 ,  G03F9/7076 ,  G03F9/708 ,  G03F9/7084 ,  H01L21/76802 ,  H01L23/544 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming contact holes using a multi-layer hard mask. A substrate with a device region and an alignment region having an opening therein to serve as an alignment mark is provided. A dielectric layer is formed overlying the substrate and fills the opening, followed by the multi-layer hard mask. The multi-layer hard mask over the opening is partially removed and that on the device region is patterned to form a plurality of holes therein and expose the underlying dielectric layer. The exposed dielectric layer on the device region is etched to form the plurality of contact holes therein.

摘要翻译： 一种使用多层硬掩模形成接触孔的方法。 提供了具有器件区域和其中具有开口的对准区域用作对准标记的衬底。 形成覆盖在基板上的电介质层，并填充开口，接着是多层硬掩模。 开口上的多层硬掩模被部分去除，并且在器件区域上被图案化以在其中形成多个孔并且暴露下面的介电层。 在器件区域上暴露的介电层被蚀刻以在其中形成多个接触孔。

公开(公告)号：US06960525B2

公开(公告)日：2005-11-01

申请号：US10437322

申请日：2003-05-13

申请人： Yi-Nan Chen ,  Hui-Min Mao

发明人： Yi-Nan Chen ,  Hui-Min Mao

IPC分类号： H01L21/285 ,  H01L21/768 ,  H01L21/4763 ,  H01L21/44

CPC分类号： H01L21/76843 ,  H01L21/28518 ,  H01L21/76802 ,  H01L21/76855

摘要： A method of forming a metal plug. First, a dielectric layer is formed on a substrate. Next, a patterned hard mask is formed on the dielectric layer. The dielectric layer is etched through the patterned hard mask to form a contact hole in the dielectric layer so as to expose parts of the substrate. An isolated layer is formed on the patterned hard mask. A barrier is then formed conformally on the isolated layer and the exposed substrate of the contact hole. A metal layer is formed to fill the contact hole and cover the barrier. A thermal treatment is performed to form a silicide between the barrier layer and the substrate. Finally, parts of the metal layer, barrier, isolated layer, and patterned hard mask are removed. The metal plug with a planar surface is thus formed in the contact hole.

摘要翻译： 一种形成金属塞的方法。 首先，在基板上形成电介质层。 接下来，在电介质层上形成图案化的硬掩模。 通过图案化的硬掩模蚀刻电介质层，以在电介质层中形成接触孔，以暴露衬底的部分。 在图案化的硬掩模上形成隔离层。 然后在隔离层和接触孔的暴露的基底上保形地形成屏障。 形成金属层以填充接触孔并覆盖屏障。 进行热处理以在阻挡层和衬底之间形成硅化物。 最后，去除金属层，阻挡层，隔离层和图案化硬掩模的部分。 因此，在接触孔中形成具有平坦表面的金属塞。