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    Fuse area structure having guard ring surrounding fuse opening in semiconductor device and method of forming the same
    11.
    发明授权
    Fuse area structure having guard ring surrounding fuse opening in semiconductor device and method of forming the same 有权
    保险丝区域结构在半导体器件中具有围绕保险丝开口的保护环及其形成方法

    公开(公告)号：US06509255B2

    公开(公告)日：2003-01-21

    申请号：US09935971

    申请日：2001-08-23

    申请人： Eun-young Minn ,  Young-hoon Park ,  Chi-hoon Lee ,  Myoung-hee Han

    发明人： Eun-young Minn ,  Young-hoon Park ,  Chi-hoon Lee ,  Myoung-hee Han

    IPC分类号： H01L2144

    CPC分类号： H01L23/5258 ,  H01L27/10894 ,  H01L27/11898 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A fuse area structure in a semiconductor device and a method of forming the same are provided. A ring-shaped guard ring which surrounds a fuse opening, for preventing moisture from seeping into the side surface of the exposed fuse opening, is included. The guard ring is integrally formed with a passivation film. In order to form the guard ring, a guard ring opening etching stop film is formed on a fuse line. A guard ring opening is formed using the etching stop film, and a contact hole is formed in a peripheral circuit. A conductive material layer for forming an upper interconnection layer is formed on the entire surface of a resultant structure on which the contact hole and the guard ring opening are formed. The conductive material layer formed on the guard ring opening is removed. The exposed etching stop film is removed. Finally, a passivation film is deposited on the entire surface of the resulting structure. Accordingly, the guard ring formed of the passivation film filling the guard ring opening is formed. It is possible to form the guard ring without an additional process, to thus effectively prevent moisture from seeping into interfaces between interlayer dielectric films. Also, an additional photolithography process for forming the guard ring is not necessary since the guard ring opening and the contact hole in the peripheral circuit are simultaneously formed.

    摘要翻译： 提供半导体器件中的熔丝区域结构及其形成方法。 包括围绕保险丝开口的环形保护环，用于防止湿气渗入暴露的保险丝开口的侧表面。 保护环与钝化膜一体形成。 为了形成保护环，在保险丝线上形成防护环开口蚀刻停止膜。 使用蚀刻停止膜形成保护环开口，并且在外围电路中形成接触孔。 在形成有接触孔和保护环开口的合成结构的整个表面上形成用于形成上互连层的导电材料层。 形成在保护环开口上的导电材料层被去除。 去除暴露的蚀刻停止膜。 最后，钝化膜沉积在所得结构的整个表面上。 因此，形成由填充保护环开口的钝化膜形成的保护环。 可以在没有附加工艺的情况下形成保护环，从而有效地防止水分渗透到层间电介质膜之间的界面中。 此外，由于保护环开口和外围电路中的接触孔同时形成，因此不需要用于形成保护环的附加光刻工艺。

    Semiconductor devices using fine patterns and methods of forming fine patterns
    13.
    发明授权
    Semiconductor devices using fine patterns and methods of forming fine patterns 有权
    使用精细图案的半导体器件和形成精细图案的方法

    公开(公告)号：US07704882B2

    公开(公告)日：2010-04-27

    申请号：US12222842

    申请日：2008-08-18

    申请人： Jeong-ho Lee ,  Young-hoon Park ,  Sang-il Jung ,  Ui-sik Kim ,  Jun-seok Yang

    发明人： Jeong-ho Lee ,  Young-hoon Park ,  Sang-il Jung ,  Ui-sik Kim ,  Jun-seok Yang

    IPC分类号： H01L21/44

    CPC分类号： H01L21/76816

    摘要： Example embodiments may provide fine patterns for semiconductor devices and methods of forming fine patterns for semiconductor devices. Example methods may include forming a spacer pattern on a substrate and/or an insulating layer pattern adjacent to sides of the spacer pattern and/or disposed at the same level as the spacer pattern, forming a pair of recesses exposing sides of the spacer pattern by removing a portion of the insulating layer pattern, and/or filling a conductive material in the recesses.

    摘要翻译： 示例性实施例可以为半导体器件提供精细图案以及为半导体器件形成精细图案的方法。 示例性方法可以包括在衬底和/或与间隔物图案的侧面相邻的基底和/或绝缘层图案上形成间隔图案和/或设置在与间隔图案相同的水平面上，形成一对凹槽，该凹槽暴露间隔图案的侧面， 去除绝缘层图案的一部分，和/或填充凹槽中的导电材料。

    Fuse area structure including protection film on sidewall of fuse opening in semiconductor device and method of forming the same
    14.
    发明授权
    Fuse area structure including protection film on sidewall of fuse opening in semiconductor device and method of forming the same 有权
    保险丝区域结构包括半导体器件中保险丝开口侧壁上的保护膜及其形成方法

    公开(公告)号：US06835998B2

    公开(公告)日：2004-12-28

    申请号：US10199538

    申请日：2002-07-19

    申请人： Chi-hoon Lee ,  Young-hoon Park ,  Hyo-dong Ban ,  Sung-hoon Kho

    发明人： Chi-hoon Lee ,  Young-hoon Park ,  Hyo-dong Ban ,  Sung-hoon Kho

    IPC分类号： H01L2900

    CPC分类号： H01L27/10894 ,  H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A fuse area structure in a semiconductor device and a method of forming the same are provided. The fuse area structure includes a protection film formed of a passivation film for preventing moisture from seeping into the sidewall of an exposed fuse opening. In order to form the protection film, an etching stop film is formed on a fuse line, and the fuse opening is formed at the same time using the etching stop film when a contact hole required for the semiconductor device is formed. A conductive material layer for forming an upper interconnection layer is formed on the entire surface of a resultant structure on which the contact hole and the fuse opening are formed. The conductive material layer formed on the fuse opening is removed. The exposed etching stop film is removed. Finally, the fuse area is completed by forming a passivation film on the entire surface of the resultant structure and removing the passivation film formed on the bottom of the fuse opening into which laser is to be irradiated. Moisture is effectively prevented from seeping into the interfaces between interlayer dielectric films since the protection film of the passivation film is formed on the sidewall of the fuse opening without an additional process. Also, an additional photolithography process for forming the fuse opening is not necessary since the fuse opening is simultaneously formed when the contact hole is formed.

    摘要翻译： 提供半导体器件中的熔丝区域结构及其形成方法。 保险丝区域结构包括由钝化膜形成的保护膜，用于防止湿气渗入暴露的保险丝开口的侧壁。 为了形成保护膜，在熔丝线上形成蚀刻停止膜，并且当形成半导体器件所需的接触孔时，使用蚀刻停止膜同时形成熔丝开口。 在形成有接触孔和保险丝开口的合成结构的整个表面上形成用于形成上互连层的导电材料层。 形成在保险丝开口上的导电材料层被去除。 去除暴露的蚀刻停止膜。 最后，通过在所得结构的整个表面上形成钝化膜并去除形成在要被照射激光的熔丝开口的底部上的钝化膜来完成保险丝区域。 由于钝化膜的保护膜形成在保险丝开口的侧壁上而没有附加的工艺，因此有效地防止了水分渗透到层间电介质膜之间的界面。 此外，由于在形成接触孔时同时形成保险丝开口，所以不需要用于形成保险丝开口的附加光刻工艺。

    Microorganism Producing Inosine and Method of Producing Inosine Using the Same
    17.
    发明申请
    Microorganism Producing Inosine and Method of Producing Inosine Using the Same 有权
    生产肌苷的微生物及使用其产生肌苷的方法

    公开(公告)号：US20100081173A1

    公开(公告)日：2010-04-01

    申请号：US12522004

    申请日：2008-01-15

    申请人： Young-hoon Park ,  Kwang-myung Cho ,  Hee-jong Lee ,  Jin-nam Lee

    发明人： Young-hoon Park ,  Kwang-myung Cho ,  Hee-jong Lee ,  Jin-nam Lee

    IPC分类号： C12P19/40 ,  C12N1/21

    CPC分类号： C12P19/32 ,  C12N9/16 ,  C12N9/2497 ,  C12P19/40 ,  C12Y302/02008

    摘要： The present invention relates to a microorganism producing inosine, which is one of purine nucleoside, an important material for 5′-inosinic acid synthesis, and method for producing inosine using the same. More particularly, the present invention relates to a recombinant microorganism of Corynebacterium genus producing inosine at high concentration by inactivating the gene encoding nucleoside hydrolase II and by enhancing the expression of the gene encoding 5′-nucleotidase, which still retains the characteristics of Corynebacterium ammoniagenes CJIP2401 (KCCM-10610).

    摘要翻译： 本发明涉及一种生产肌苷的微生物，其是嘌呤核苷之一，是5'-肌苷酸合成的重要材料，以及使用其的产生肌苷的方法。 更具体地说，本发明涉及通过使编码核苷水解酶II的基因失活而产生高浓度肌苷的棒杆菌属的重组微生物，并且通过增强仍保留产氨棒杆菌CJIP2401的特征的编码5'-核苷酸酶的基因的表达， （KCCM-10610）。

    Integrated circuit chip having anti-moisture-absorption film at edge thereof and method of forming anti-moisture-absorption film
    19.
    发明授权
    Integrated circuit chip having anti-moisture-absorption film at edge thereof and method of forming anti-moisture-absorption film 有权
    在其边缘具有抗吸湿膜的集成电路芯片和形成抗吸湿膜的方法

    公开(公告)号：US06696353B2

    公开(公告)日：2004-02-24

    申请号：US10396902

    申请日：2003-03-25

    申请人： Eun-young Minn ,  Young-hoon Park ,  Chi-Hoon Lee ,  Hyo-dong Ban

    发明人： Eun-young Minn ,  Young-hoon Park ,  Chi-Hoon Lee ,  Hyo-dong Ban

    IPC分类号： H01L21301

    CPC分类号： H01L23/26 ,  H01L23/3178 ,  H01L2924/0002 ,  H01L2924/19041 ,  H01L2924/00

    摘要： An integrated circuit chip having an anti-moisture-absorption film at the edge thereof and a method of forming the anti-moisture-absorption film are provided. In the integrated circuit chip which has predetermined devices inside and whose uppermost layer is covered with a passivation film, a trench is formed by etching interlayer dielectric films to a predetermined depth along the perimeter of the integrated circuit chip to be adjacent to the edge of the integrated circuit chip and an anti-moisture-absorption film is formed to fill the trench or is formed on the sidewall of the trench to a predetermined thickness, in order to prevent moisture from seeping into the edge of the integrated circuit chip. Moisture is effectively prevented from seeping into the edge of the chip by forming the anti-moisture-absorption film at the edge of the chip using the conventional processes of manufacturing the integrated circuit chip without an additional process.

    摘要翻译： 提供了在其边缘具有抗吸湿膜的集成电路芯片和形成抗吸湿膜的方法。 在内部具有预定的器件并且其最上层被钝化膜覆盖的集成电路芯片中，通过沿着集成电路芯片的周边将层间绝缘膜蚀刻到预定深度以形成沟槽，以与 形成集成电路芯片和防潮湿吸收膜以填充沟槽或形成在沟槽的侧壁上至预定厚度，以防止湿气渗入集成电路芯片的边缘。 通过使用制造集成电路芯片的常规工艺在芯片的边缘处形成防潮湿吸收膜而无需额外的工艺，有效地防止了水分渗透到芯片的边缘。

    Bonding pad structures for semiconductor devices and fabrication methods thereof
    20.
    发明授权
    Bonding pad structures for semiconductor devices and fabrication methods thereof 失效
    用于半导体器件的接合焊盘结构及其制造方法

    公开(公告)号：US06465895B1

    公开(公告)日：2002-10-15

    申请号：US09826590

    申请日：2001-04-05

    申请人： Young-hoon Park ,  Eun-young Min ,  Weon-cheol Hong

    发明人： Young-hoon Park ,  Eun-young Min ,  Weon-cheol Hong

    IPC分类号： H01L2348

    CPC分类号： H01L24/05 ,  H01L24/48 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05093 ,  H01L2224/05095 ,  H01L2224/05556 ,  H01L2224/05599 ,  H01L2224/05624 ,  H01L2224/05666 ,  H01L2224/48463 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2224/45099

    摘要： The present invention is directed to a semiconductor structure, and a fabrication technique for forming such a structure, configured to confine and prevent expansion of cracking of the insulating layer below a bonding pad, that are generated as a result of the bonding process. In a first embodiment, the present invention includes a vertical frame, formed, for example of conductive material, surrounding the outer perimeter of the bonding pad, and extending through an underlying insulating layer. A horizontal frame lies below the vertical frame. Together, the vertical frame and horizontal frame confine cracks emanating below the bonding pad to within the frame region. In a second embodiment, horizontal and vertical portions of the frame are formed by a conductive layer provided in an opening formed in the insulating layer. Since the isolation frame prevents cracks from expanding into surrounding regions of the integrated circuit, overall process yield and reliability are improved.

    摘要翻译： 本发明涉及一种用于形成这种结构的半导体结构和制造技术，其被配置为限制并防止由于接合工艺而产生的绝缘层在焊盘下方的开裂的膨胀。 在第一实施例中，本发明包括垂直框架，其例如由导电材料形成，围绕焊盘的外周边并延伸穿过下面的绝缘层。 水平框架位于垂直框架下方。 垂直框架和水平框架一起将焊接垫下方的裂纹限制在框架区域内。 在第二实施例中，框架的水平和垂直部分由设置在绝缘层中形成的开口中的导电层形成。 由于隔离框架防止裂纹扩展到集成电路的周围区域，因此整体工艺产量和可靠性得到改善。