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11.发明申请Polymeric tetrahedral carbon films, methods of forming the same and methods of forming fine patterns using the same 审中-公开聚合四面体碳膜，其形成方法和使用其形成精细图案的方法公开(公告)号：US20060115772A1
公开(公告)日：2006-06-01
申请号：US11282368
申请日：2005-11-18
申请人： Jung-Hwan Hah , Yool Kang , Man-Hyoung Ryoo , Shi-Yong Yi , Sang-Gyun Woo
发明人： Jung-Hwan Hah , Yool Kang , Man-Hyoung Ryoo , Shi-Yong Yi , Sang-Gyun Woo
IPC分类号： G03C5/00
摘要： The present invention provides polymeric films including polymers having an sp3 carbon main frame including a tetrahedral center atom. Methods of forming the same, hard marks including the same and methods of forming fine patterns using the same are also provided.
摘要翻译： 本发明提供了聚合物膜，其包括具有包含四面体中心原子的sp 3 O 3碳主框的聚合物。 还提供了形成它们的方法，包括其的硬标记和使用其形成精细图案的方法。
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12.发明授权Biosensor using nanoscale material as transistor channel and method of fabricating the same 有权使用纳米级材料作为晶体管沟道的生物传感器及其制造方法公开(公告)号：US08013366B2
公开(公告)日：2011-09-06
申请号：US12232243
申请日：2008-09-12
申请人： Moon-Sook Lee , Byeong-Ok Cho , Man-Hyoung Ryoo , Takahiro Yasue , Jung-Hwan Hah
发明人： Moon-Sook Lee , Byeong-Ok Cho , Man-Hyoung Ryoo , Takahiro Yasue , Jung-Hwan Hah
IPC分类号： G01N27/403 , H01L21/00
CPC分类号： G01N27/4145 , B82Y10/00 , B82Y15/00 , G01N27/4146 , H01L51/0595 , H01L2924/0002 , H01L2924/00
摘要： Example embodiments relate to a biosensor using a nanoscale material as a channel of a transistor and a method of fabricating the same. A biosensor according to example embodiments may include a plurality of insulating films. A first signal line and a second signal line may be interposed between the plurality of insulating films. A semiconductor nanostructure may be disposed on the plurality of insulating films, the semiconductor nanostructure having a first side electrically connected to the first signal line and a second side electrically connected to the second signal line. A plurality of probes may be coupled to the semiconductor nanostructure. A biosensor according to example embodiments may have a reduced analysis time.
摘要翻译： 实施例涉及使用纳米级材料作为晶体管的沟道的生物传感器及其制造方法。 根据示例性实施例的生物传感器可以包括多个绝缘膜。 第一信号线和第二信号线可以插入在多个绝缘膜之间。 半导体纳米结构可以设置在多个绝缘膜上，半导体纳米结构具有电连接到第一信号线的第一侧和与第二信号线电连接的第二侧。 多个探针可以耦合到半导体纳米结构。 根据示例性实施例的生物传感器可以具有减少的分析时间。
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公开(公告)号：US08338815B2
公开(公告)日：2012-12-25
申请号：US12851268
申请日：2010-08-05
申请人： Moon-Sook Lee , Byeong-Ok Cho , Man-Hyoung Ryoo , Takahiro Yasue
发明人： Moon-Sook Lee , Byeong-Ok Cho , Man-Hyoung Ryoo , Takahiro Yasue
CPC分类号： H01L27/11507 , B82Y10/00 , H01L27/10 , H01L27/1021 , H01L27/24
摘要： Methods of fabricating a memory unit are provided including forming a plurality of first nanowire structures, each of which includes a first nanowire extending in a first direction parallel to the first substrate and a first electrode layer enclosing the first nanowire, on a first substrate. The first electrode layers are partially removed to form first electrodes beneath the first nanowires. A first insulation layer filling up spaces between structures, each of which includes the first nanowire and the first electrode, is formed on the first substrate. A second electrode layer is formed on the first nanowires and the first insulation layer. A plurality of second nanowires is formed on the second electrode layer, each of which extends in a second direction perpendicular to the first direction. The second electrode layer is partially etched using the second nanowires as an etching mask to form a plurality of second electrodes. Related memory units, methods of fabricating semiconductor devices and semiconductor devices are also provided.
摘要翻译： 提供了一种制造存储器单元的方法，包括形成多个第一纳米线结构，每个第一纳米线结构包括在第一衬底上沿与第一衬底平行的第一方向延伸的第一纳米线和包围第一纳米线的第一电极层。 第一电极层被部分地去除以在第一纳米线下方形成第一电极。 填充第一基板上形成有第一纳米线和第一电极的结构之间的空间的第一绝缘层。 在第一纳米线和第一绝缘层上形成第二电极层。 多个第二纳米线形成在第二电极层上，每个第二纳米线沿垂直于第一方向的第二方向延伸。 使用第二纳米线作为蚀刻掩模来部分蚀刻第二电极层以形成多个第二电极。 还提供了相关的存储单元，制造半导体器件和半导体器件的方法。
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公开(公告)号：US20090189152A1
公开(公告)日：2009-07-30
申请号：US12354990
申请日：2009-01-16
CPC分类号： H01L29/78391 , B82Y10/00 , G11C11/22 , H01L29/40111 , H01L29/516 , H01L29/6684
摘要： Provided is a ferroelectric memory device. The ferroelectric memory device includes an inorganic channel pattern on a substrate, a source electrode and a drain electrode spaced apart from each other on the substrate and contacting the inorganic channel pattern, a gate electrode disposed adjacent to the inorganic channel pattern, and an organic ferroelectric layer interposed between the inorganic channel pattern and the gate electrode.
摘要翻译： 提供了一种铁电存储器件。 铁电存储器件包括在衬底上的无机沟道图案，在衬底上彼此间隔开的源电极和漏电极，并与无机沟道图案接触，邻近无机沟道图案设置的栅电极和有机铁电体 介于无机通道图案和栅电极之间的层。
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15.发明申请Integrated circuit semiconductor device with overlay key and alignment key and method of fabricating the same 有权具有覆盖键和对准键的集成电路半导体器件及其制造方法公开(公告)号：US20050031995A1
公开(公告)日：2005-02-10
申请号：US10867468
申请日：2004-06-14
IPC分类号： G03F9/00 , G03F7/00 , G03F7/20 , H01L21/027 , H01L23/544
CPC分类号： H01L23/544 , G03F7/70633 , G03F9/7076 , G03F9/708 , G03F9/7084 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit semiconductor device including a cell region formed in a first portion of a silicon substrate, the cell region including a first trench formed in the silicon substrate, a first buried insulating layer filled in the first trench, a first insulating pattern formed over the silicon substrate, and a first conductive pattern formed over the first insulating pattern. An overlay key region is formed in a second portion of the silicon substrate and includes a second trench formed in the silicon substrate, a second insulating pattern formed over the silicon substrate and used as an overlay key, and a second conductive pattern formed over the second insulating pattern and formed by correcting overlay and alignment errors using the second insulating pattern. An alignment key region is formed in a third portion of the silicon substrate and includes a third trench formed in the silicon substrate and used as an alignment key, a second buried insulating layer formed in the third trench, and a third conductive pattern formed over the second buried insulating layer and the third trench.
摘要翻译： 一种集成电路半导体器件，包括形成在硅衬底的第一部分中的单元区域，所述单元区域包括形成在所述硅衬底中的第一沟槽，填充在所述第一沟槽中的第一掩埋绝缘层，形成在所述第一沟槽上的第一绝缘图案 硅衬底和形成在第一绝缘图案上的第一导电图案。 覆盖键区域形成在硅衬底的第二部分中，并且包括在硅衬底中形成的第二沟槽，形成在硅衬底上并用作覆盖键的第二绝缘图案，以及形成在第二衬底上的第二导电图案 绝缘图案，并且通过使用第二绝缘图案校正覆盖和对准误差而形成。 对准键区域形成在硅衬底的第三部分中，并且包括形成在硅衬底中并用作对准键的第三沟槽，形成在第三沟槽中的第二掩埋绝缘层和形成在第三沟槽上的第三导电图案 第二掩埋绝缘层和第三沟槽。
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16.发明申请Semiconductor device having sufficient process margin and method of forming same 有权具有足够的加工余量的半导体器件及其形成方法公开(公告)号：US20050012157A1
公开(公告)日：2005-01-20
申请号：US10892588
申请日：2004-07-15
申请人： Man-Hyoung Ryoo , Gi-Sung Yeo , Si-Hyeung Lee , Gyu-Chul Kim , Sung-Gon Jung , Chang-Min Park , Hoo-Sung Cho
发明人： Man-Hyoung Ryoo , Gi-Sung Yeo , Si-Hyeung Lee , Gyu-Chul Kim , Sung-Gon Jung , Chang-Min Park , Hoo-Sung Cho
IPC分类号： G11C11/34 , G11C11/412 , H01L27/02 , H01L27/11
CPC分类号： H01L27/088 , G11C11/412 , H01L27/0203 , H01L27/1104 , Y10S257/903
摘要： According to some embodiments of the invention, a substrate doped with a P type impurity is provided. An N type impurity is doped into the substrate to divide the substrate into a P type impurity region and an N type impurity region. Active patterns having a first pitch are formed in the P type and N type impurity regions. Gate patterns having a second pitch are formed on the active patterns in a direction substantially perpendicular to the active patterns. Other embodiments are described and claimed.
摘要翻译： 根据本发明的一些实施例，提供掺杂有P型杂质的衬底。 在衬底中掺杂N型杂质以将衬底分成P型杂质区和N型杂质区。 在P型和N型杂质区中形成具有第一间距的有源图案。 具有第二间距的栅极图案在与有源图案基本垂直的方向上形成在有源图案上。 描述和要求保护其他实施例。
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17.发明授权Semiconductor device having sufficient process margin and method of forming same 有权具有足够的加工余量的半导体器件及其形成方法公开(公告)号：US08193047B2
公开(公告)日：2012-06-05
申请号：US12654798
申请日：2010-01-04
申请人： Man-Hyoung Ryoo , Gi-Sung Yeo , Si-Hyeung Lee , Gyu-Chul Kim , Sung-Gon Jung , Chang-Min Park , Hoo-Sung Cho
发明人： Man-Hyoung Ryoo , Gi-Sung Yeo , Si-Hyeung Lee , Gyu-Chul Kim , Sung-Gon Jung , Chang-Min Park , Hoo-Sung Cho
IPC分类号： H01L21/8239
CPC分类号： H01L27/088 , G11C11/412 , H01L27/0203 , H01L27/1104 , Y10S257/903
摘要： According to some embodiments of the invention, a substrate doped with a P type impurity is provided. An N type impurity is doped into the substrate to divide the substrate into a P type impurity region and an N type impurity region. Active patterns having a first pitch are formed in the P type and N type impurity regions. Gate patterns having a second pitch are formed on the active patterns in a direction substantially perpendicular to the active patterns. Other embodiments are described and claimed.
摘要翻译： 根据本发明的一些实施例，提供掺杂有P型杂质的衬底。 在衬底中掺杂N型杂质以将衬底分成P型杂质区和N型杂质区。 在P型和N型杂质区中形成具有第一间距的有源图案。 具有第二间距的栅极图案在与有源图案基本垂直的方向上形成在有源图案上。 描述和要求保护其他实施例。
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18.发明授权Integrated circuit semiconductor device with overlay key and alignment key and method of fabricating the same 有权具有覆盖键和对准键的集成电路半导体器件及其制造方法公开(公告)号：US08080886B2
公开(公告)日：2011-12-20
申请号：US12111651
申请日：2008-04-29
IPC分类号： H01L23/544
CPC分类号： H01L23/544 , G03F7/70633 , G03F9/7076 , G03F9/708 , G03F9/7084 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit semiconductor device including a cell region formed in a first portion of a silicon substrate, the cell region including a first trench formed in the silicon substrate, a first buried insulating layer filled in the first trench, a first insulating pattern formed over the silicon substrate, and a first conductive pattern formed over the first insulating pattern. An overlay key region is formed in a second portion of the silicon substrate and includes a second trench formed in the silicon substrate, a second insulating pattern formed over the silicon substrate and used as an overlay key, and a second conductive pattern formed over the second insulating pattern and formed by correcting overlay and alignment errors using the second insulating pattern. An alignment key region is formed in a third portion of the silicon substrate and includes a third trench formed in the silicon substrate and used as an alignment key, a second buried insulating layer formed in the third trench, and a third conductive pattern formed over the second buried insulating layer and the third trench.
摘要翻译： 一种集成电路半导体器件，包括形成在硅衬底的第一部分中的单元区域，所述单元区域包括形成在所述硅衬底中的第一沟槽，填充在所述第一沟槽中的第一掩埋绝缘层，形成在所述第一沟槽上的第一绝缘图案 硅衬底和形成在第一绝缘图案上的第一导电图案。 覆盖键区域形成在硅衬底的第二部分中，并且包括在硅衬底中形成的第二沟槽，形成在硅衬底上并用作覆盖键的第二绝缘图案，以及形成在第二衬底上的第二导电图案 绝缘图案，并且通过使用第二绝缘图案校正覆盖和对准误差而形成。 对准键区域形成在硅衬底的第三部分中，并且包括形成在硅衬底中并用作对准键的第三沟槽，形成在第三沟槽中的第二掩埋绝缘层和形成在第三沟槽上的第三导电图案 第二掩埋绝缘层和第三沟槽。
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19.发明授权Integrated circuit semiconductor device with overlay key and alignment key and method of fabricating the same 有权具有覆盖键和对准键的集成电路半导体器件及其制造方法公开(公告)号：US07381508B2
公开(公告)日：2008-06-03
申请号：US10867468
申请日：2004-06-14
CPC分类号： H01L23/544 , G03F7/70633 , G03F9/7076 , G03F9/708 , G03F9/7084 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit semiconductor device including a cell region formed in a first portion of a silicon substrate, the cell region including a first trench formed in the silicon substrate, a first buried insulating layer filled in the first trench, a first insulating pattern formed over the silicon substrate, and a first conductive pattern formed over the first insulating pattern. An overlay key region is formed in a second portion of the silicon substrate and includes a second trench formed in the silicon substrate, a second insulating pattern formed over the silicon substrate and used as an overlay key, and a second conductive pattern formed over the second insulating pattern and formed by correcting overlay and alignment errors using the second insulating pattern. An alignment key region is formed in a third portion of the silicon substrate and includes a third trench formed in the silicon substrate and used as an alignment key, a second buried insulating layer formed in the third trench, and a third conductive pattern formed over the second buried insulating layer and the third trench.
摘要翻译： 一种集成电路半导体器件，包括形成在硅衬底的第一部分中的单元区域，所述单元区域包括形成在所述硅衬底中的第一沟槽，填充在所述第一沟槽中的第一掩埋绝缘层，形成在所述第一沟槽上的第一绝缘图案 硅衬底和形成在第一绝缘图案上的第一导电图案。 覆盖键区域形成在硅衬底的第二部分中，并且包括在硅衬底中形成的第二沟槽，形成在硅衬底上并用作覆盖键的第二绝缘图案，以及形成在第二衬底上的第二导电图案 绝缘图案，并且通过使用第二绝缘图案校正覆盖和对准误差而形成。 对准键区域形成在硅衬底的第三部分中，并且包括形成在硅衬底中并用作对准键的第三沟槽，形成在第三沟槽中的第二掩埋绝缘层和形成在第三沟槽上的第三导电图案 第二掩埋绝缘层和第三沟槽。
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20.发明授权Semiconductor device having sufficient process margin and method of forming same 有权具有足够的加工余量的半导体器件及其形成方法公开(公告)号：US07221031B2
公开(公告)日：2007-05-22
申请号：US10892588
申请日：2004-07-15
申请人： Man-Hyoung Ryoo , Gi-Sung Yeo , Si-Hyeung Lee , Gyu-Chul Kim , Sung-Gon Jung , Chang-Min Park , Hoo-Sung Cho
发明人： Man-Hyoung Ryoo , Gi-Sung Yeo , Si-Hyeung Lee , Gyu-Chul Kim , Sung-Gon Jung , Chang-Min Park , Hoo-Sung Cho
IPC分类号： H01L27/11
CPC分类号： H01L27/088 , G11C11/412 , H01L27/0203 , H01L27/1104 , Y10S257/903
摘要： According to some embodiments of the invention, a substrate doped with a P type impurity is provided. An N type impurity is doped into the substrate to divide the substrate into a P type impurity region and an N type impurity region. Active patterns having a first pitch are formed in the P type and N type impurity regions. Gate patterns having a second pitch are formed on the active patterns in a direction substantially perpendicular to the active patterns. Other embodiments are described and claimed.
摘要翻译： 根据本发明的一些实施例，提供掺杂有P型杂质的衬底。 在衬底中掺杂N型杂质以将衬底分成P型杂质区和N型杂质区。 在P型和N型杂质区中形成具有第一间距的有源图案。 具有第二间距的栅极图案在与有源图案基本垂直的方向上形成在有源图案上。 描述和要求保护其他实施例。
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