公开(公告)号：US11323108B1

公开(公告)日：2022-05-03

申请号：US17107572

申请日：2020-11-30

Applicant: XILINX, INC.

Inventor： Bob W. Verbruggen ,  Christophe Erdmann ,  Ionut C. Cical

IPC: H04L25/02 ,  H03K5/133 ,  H03K3/037 ,  H05K1/02 ,  G06F13/40

Abstract: A low current line termination circuit includes first and second input interfaces each configured to receive a Vreceive+ and a Vreceive− voltage, respectively. The circuit further includes a first diode connected transistor (“DCT”) coupled to the second input interface, a first switching transistor (“ST”) coupled to the first DCT and to the first input interface, and a first delay element coupled between one of the input interfaces and a gate of the first ST. The circuit further includes a second DCT coupled to the one of the two input interfaces, a second ST coupled to the second DCT and to the second input interface, and a second delay element coupled between another of the two input interfaces and a gate of the second ST.

公开(公告)号：US11009597B2

公开(公告)日：2021-05-18

申请号：US16222801

申请日：2018-12-17

Applicant: Xilinx, Inc.

Inventor： Brendan Farley ,  Christophe Erdmann ,  Bob W. Verbruggen

IPC: G01S13/50 ,  G01S13/90 ,  G01S13/58

Abstract: A radar system includes a transmitter to transmit a sequence of pulses, a receiver to receive reflections of the transmitted pulses, and velocity detection circuitry to determine a velocity of an object in a path of the transmitted pulses based at least in part on the transmitted pulses and the reflected pulses. The transmitter includes a plurality of digital-to-analog converters (DACs) to generate the sequence of pulses in response to a clock signal. The receiver includes a plurality of analog-to-digital converters (ADCs) to sample the reflected pulses in response to the clock signal. Accordingly, the ADCs are locked in phase with the DACs.

公开(公告)号：US10483996B1

公开(公告)日：2019-11-19

申请号：US15991539

申请日：2018-05-29

Applicant: Xilinx, Inc.

Inventor： Christophe Erdmann ,  Bob W. Verbruggen ,  Ali Boumaalif ,  Bruno Miguel Vaz

IPC: H03M1/12 ,  G06F1/10 ,  H03M1/66 ,  H03M1/06

Abstract: Apparatus and associated methods relate to modulating polarity on sample outputs from a time-interleaved analog-to-digital converter (TIADC) as an input to a time skew extractor in a clock skew calibration control loop. In an illustrative example, a multiplier-mixer may impart a polarity change to every other data sample transmitted between the TIADC and the time skew extractor. In some examples, a multiplexer may select between the polarity modulated samples and non-polarity modulated samples before the multiplier-mixer. Selection between the polarity modulated samples and the non-polarity modulated samples may be based on, for example, determination of specific frequency bands of an analog input signal. Various embodiments may improve convergence of clock skew calibration control loops for analog input signals sampled with a TIADC near a Nyquist frequency.

公开(公告)号：US10298248B1

公开(公告)日：2019-05-21

申请号：US15912318

申请日：2018-03-05

Applicant: Xilinx, Inc.

Inventor： Bruno Miguel Vaz ,  Christophe Erdmann ,  Bob W. Verbruggen ,  John E. McGrath ,  Ali Boumaalif

IPC: H03M1/10 ,  H03M1/12 ,  H03K19/177

Abstract: An example apparatus for analog-to-digital conversion includes a plurality of channels each including an analog-to-digital converter (ADC), a switch configured to couple a differential input to the ADC, a first offset calibration circuit coupled to an output of the ADC, a multiplier coupled to an output of the first offset calibration circuit, a second offset calibration circuit coupled to an output of the multiplier, and a pseudorandom bit sequence (PRBS) generator coupled to the switch and the multiplier. The apparatus further includes a gain calibration circuit coupled to an output of the second offset calibration circuit in each of the plurality of channels; and a time-skew calibration circuit coupled to an output of the gain calibration circuit.

公开(公告)号：US10291247B1

公开(公告)日：2019-05-14

申请号：US15914364

申请日：2018-03-07

Applicant: Xilinx, Inc.

Inventor： Bob W. Verbruggen ,  Christophe Erdmann ,  Bruno Miguel Vaz

IPC: H03M1/06 ,  H03M1/10 ,  H03M1/12

Abstract: An example time-skew calibration circuit includes a plurality of first circuits, each including a first accumulator and a second accumulator. The time-skew calibration circuit further includes a plurality of second circuits, each including a first adder coupled to outputs of the first accumulator and the second accumulator, and a first subtractor coupled to the outputs of the first accumulator and the second accumulator. The time-skew calibration circuit further includes a decision circuit configured to combine an output of the first adder and an output of the first subtractor.

公开(公告)号：US20190115926A1

公开(公告)日：2019-04-18

申请号：US15784022

申请日：2017-10-13

Applicant: Xilinx, Inc.

Inventor： Augusto R. Ximenes ,  Bob W. Verbruggen ,  Christophe Erdmann

IPC: H03L7/091 ,  H03L7/099

Abstract: An example digital-to-time converter (DTC) includes: a delay chain circuit having a plurality of delay cells coupled in sequence, the delay chain circuit including a first input to receive a first clock signal and a second input to receive a second clock signal; and a DEM controller coupled to the delay chain circuit to provide a plurality of control signals to the plurality of delay cells, respectively.

公开(公告)号：US09054096B2

公开(公告)日：2015-06-09

申请号：US13626829

申请日：2012-09-25

Applicant: Xilinx, Inc.

Inventor： Christophe Erdmann ,  Edward Cullen ,  Donnacha Lowney

IPC: H01L23/552 ,  H01L23/498 ,  H01L23/66 ,  H01L23/538 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/49827 ,  H01L23/5382 ,  H01L23/5384 ,  H01L23/552 ,  H01L23/66 ,  H01L24/16 ,  H01L25/0655 ,  H01L2223/6622 ,  H01L2224/16225 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311

Abstract: An embodiment of an apparatus is disclosed. For this embodiment of the apparatus, an interposer has first vias. First interconnects and second interconnects respectively are coupled on opposite surfaces of the interposer. A first portion of the first interconnects and a second portion of the first interconnects are spaced apart from one another defining an isolation region between them. A substrate has second vias. Third interconnects and the second interconnects are respectively coupled on opposite surfaces of the package substrate. A first portion of the first vias and a first portion of the second vias are both in the isolation region and are coupled to one another with a first portion of the second interconnects.

Abstract translation: 公开了一种装置的实施例。 对于该装置的该实施例，插入器具有第一通孔。 第一互连和第二互连分别耦合在插入器的相对表面上。 第一互连的第一部分和第一互连的第二部分彼此间隔开，在它们之间限定隔离区。 衬底具有第二通孔。 第三互连和第二互连分别耦合在封装衬底的相对表面上。 第一通孔的第一部分和第二通孔的第一部分都在隔离区域中并且彼此耦合，具有第二互连的第一部分。

公开(公告)号：US09035815B1

公开(公告)日：2015-05-19

申请号：US14197003

申请日：2014-03-04

Applicant: Xilinx, Inc.

Inventor： Donnacha Lowney ,  Aidan Keady ,  Christophe Erdmann

IPC: H03M1/50

CPC classification number: H03M1/50 ,  G04F10/005 ,  H03M1/12

Abstract: An apparatus relating generally to signal analysis is disclosed. In such an apparatus, a first comparator is coupled to receive a signal input and a first input level. A second comparator is coupled to receive the signal input and a second input level different from the first input level. A time-to-digital converter is coupled at a first port thereof, such as a start port for example, to receive a first output from the first comparator and coupled at a second port thereof, such as a stop port for example, to receive a second output from the second comparator. The time-to-digital converter is coupled to provide digital words representing the signal input.

Abstract translation: 公开了一般涉及信号分析的装置。 在这种装置中，第一比较器被耦合以接收信号输入和第一输入电平。 第二比较器被耦合以接收信号输入和不同于第一输入电平的第二输入电平。 时间数字转换器在其第一端口（例如起始端口）处耦合，以接收来自第一比较器的第一输出，并在其第二端口（例如停止端口）处耦合以接收 来自第二比较器的第二输出。 时间 - 数字转换器被耦合以提供表示信号输入的数字字。

公开(公告)号：US12237829B2

公开(公告)日：2025-02-25

申请号：US18086534

申请日：2022-12-21

Applicant: XILINX, INC.

Inventor： Abhirup Lahiri ,  Christophe Erdmann

IPC: H03M1/12 ,  H03K17/687 ,  H03K5/00 ,  H03K5/01

Abstract: An electronic system includes a source follower circuitry that functions as an input driver. The source follower circuitry includes a first input transistor, first current source circuitry, and first phase shift circuitry. The first input transistor includes a first node coupled to a first voltage node, a second node coupled to a first output node, and a gate node coupled to a first input node. The gate node receives a first input signal via the first input node. The first current source circuitry coupled to the first output node and configured to generate a first bias current. The first phase shift circuitry is coupled to the first current source circuitry. The first phase shift circuitry generates a first phase shift signal to modulate the first current source circuitry to reduce signal drop across the first input transistor.

公开(公告)号：US20240213995A1

公开(公告)日：2024-06-27

申请号：US18088982

申请日：2022-12-27

Applicant: Xilinx, Inc.

Inventor： Bob Verbruggen ,  Christophe Erdmann

IPC: H03M1/10

CPC classification number: H03M1/1014

Abstract: Methods and apparatus for calibrating a gain for a circuit block are disclosed. An example method includes receiving a plurality of quantizer offsets, where the plurality of quantizer offsets represent calibration data for a quantizer configured to quantize an output of the circuit block, determining one or more differences based on one or more first quantizer offsets of the plurality of quantizer offsets and on one or more second quantizer offsets of the plurality of quantizer offsets, and determining an incremental change in a gain associated with the circuit block based on the one or more differences.